- Added build_hp_rtthread.py for building the RT-Thread kernel with RV64 support.
- Updated build_hp_smoke.py to target RV64 architecture and modified output filenames.
- Modified generate_vexiiriscv.py to reflect RV64 configuration and memory management.
- Created hp_tools.py for shared utilities related to RV64 builds.
- Enhanced package_hp_boot.py to package RV64 workloads and updated versioning.
- Implemented run_hp_sim.py for executing and validating HP workloads with specific markers.
- Developed setup_hp_rtthread.py for installing RT-Thread source and environment setup.
- Updated GenerateRetroSocHp.scala to generate RV64 application cores.
- Enhanced tests for HP boot bundles, platform specifications, and tool utilities to accommodate RV64 changes.
- Adjusted test cases to validate new workload types and ensure compatibility with RV64 architecture.
- Introduced to validate AXI4 interface for 64-bit on-chip SRAM.
- Added to test resource controller functionality including ownership, IRQ handling, and cache handshake.
- Updated to include resource controller interface.
- Enhanced to cover additional IRQ scenarios.
- Added new tests in for AXI4 target guard timeout and isolation.
- Updated to reflect changes in the high-performance profile.
- Modified to verify on-chip SRAM bank configurations.
- Added for directed verification of resource controller.
- Updated to check SDRAM mapped window coverage.
- Enhanced to ensure correct IRQ mappings and APB target generation.
- Added interface to and implemented error handling for register writes.
- Introduced a new test for AXI4 address gate functionality in .
- Updated clock and reset domain assertions in to reflect new domain names.
- Modified expected outputs in to include new clock domains.
- Adjusted chip configuration assertions in to account for additional power pads.
- Enhanced memory map tests in with new definitions and includes.
- Updated pin mapping tests in to include new reference clock pads.
- Improved script tools tests in to ensure correct validation of extension bindings.
- Refined system control tests in to include new clock control interface.
- Updated USB2 packet RAM tests in to include new SRAM definitions.
- Enhanced user extensions tests in to validate new product extension configurations.
- Adjusted user IP register parity tests to use legacy extensions.
- Updated Yosys synthesis recipe tests to reflect changes in STA period calculations.
- Updated axi4_interconnect_tb to include an additional master and issue high-priority access tests.
- Introduced hp_mailbox_tb for testing the HP mailbox functionality, including register and doorbell operations.
- Added plic_tb to validate PLIC priority, claim, and completion mechanisms.
- Enhanced pll_ctrl_tb to initialize additional system control signals.
- Updated soc_irq_topology_tb to account for new IRQ sources and validate IRQ signal behavior.
- Improved sysctrl_tb to include tests for HP lifecycle control and status registers.
- Added tests for HP boot bundle layout, CRC, and payload validation.
- Introduced test_hp_mailbox.py for RTL regression testing of the HP mailbox.
- Added test_hp_platform.py to validate HP platform configuration and generated-source boundaries.
- Enhanced test_librelane_flow.py to ensure correct signal placement in chip configuration.
- Added performance log tests to validate LP and HP coremark ratios.
- Updated test_soc_topology.py to reflect changes in IRQ and peripheral mappings.
maksyuki