admin/retroSoC
1
0 Fork 0
mirror of https://github.com/retroSoC/retroSoC.git synced 2026-11-06 14:55:14 +00:00
Code Issues Packages Projects Releases Wiki Activity
1,066 Commits 8 Branches 0 Tags
5c65fcca27fdd8d08b41615c604eb2b6d78c0f08
Commit Graph
3 Commits
Author SHA1 Message Date
maksyuki e86187a5f3 feat: enhance DMA functionality with TCD and CRC support 
- Added TCD head and count registers to DMA definition and register files.
- Introduced CRC expected and result registers for enhanced error checking.
- Updated DMA version to 2.0 to reflect new features.
- Modified DMA testbench to validate new TCD and CRC functionalities.
- Enhanced README and filelists to include new dependencies and configurations.
- Updated formal verification and runtime tests to accommodate new DMA features.
 2026-08-28 08:42:36 +08:00
maksyuki db9282aaf6 feat: add crypto accelerator support and related tests 
- Modified DMA error testbench to include crypto input and output AXI4 stream interfaces.
- Updated DMA register testbench to integrate crypto AXI4 stream interfaces.
- Enhanced SOC IRQ topology test to account for new crypto IRQs.
- Added WS2812 DMA testbench modifications for crypto interfaces.
- Introduced new Python tests for crypto primitives (AES, SHA, RSA) and APB register paths.
- Implemented register parity tests to ensure synchronization between RTL and SDK constants.
- Expanded DMA tests to validate crypto streaming endpoints.
- Updated memory map tests to include crypto address definitions.
- Adjusted SOC topology tests to reflect changes in IRQ mappings and peripheral counts.
 2026-08-21 07:29:00 +08:00
maksyuki dd3cb6ff5c feat: add formal verification properties for DMA design and corresponding testbench 
- Introduced  to define formal properties for the DMA design, ensuring correct behavior under various conditions.
- Created  as a testbench for the DMA register interface, implementing APB and AXI4 protocols to validate register operations.
- Added  to verify synchronization between RTL and SDK register constants, ensuring consistency across implementations.
 2026-08-18 16:54:55 +08:00