- Updated filelist to include sg13g2_udp.v for IHP130.
- Modified sdram_axi4.sv to initialize read and write control signals.
- Enhanced clock and reset domain configuration to include jtag_trst_n_i_pad.
- Updated iverilog.mk to support IHP130 in tech-cell-test.
- Enhanced pin_map generation to include power pads for IHP130.
- Updated tc_io modules to handle power pins for IHP130.
- Added timing contract generation in package.py for commercial flow.
- Enhanced test cases to validate new IHP130 features and configurations.
- Added new tests for LibreLane flow specific to IHP130.
- Introduced and for STA flow, enabling scenario loading and timing analysis.
- Added for synthesis flow, defining the synthesis process and generating reports.
- Implemented for synthesis, including library handling and design checks.
- Enhanced to support additional filelists and include directories for SOC export.
- Added ICS55 PLL implementation in with corresponding testbench .
- Created comprehensive tests in for various flow components and scenarios.
- Updated to forward new filelist arguments for SOC generation.
- Improved to validate source export functionality and ensure proper file handling.
maksyuki