- Introduced for independent mathematical operations and RSA fixtures.
- Implemented for testing DMA channels with AES ECB and memory interactions.
- Created to validate RSA-2048 operations and Montgomery reduction.
- Developed for testing AES and SHA vector compliance.
- Added to validate image packing, integer root calculations, and inventory checks.
- Ensured robust error handling and validation in tests to catch data corruption and recursive hierarchy issues.
- Introduced for deterministic corpus framing, CRC checks, and regression evidence for NPU-P6.
- Added to validate NPU-P6 reference execution.
- Created a new RTL model for gate-level NPU transactions.
- Updated to instantiate and streamline the testbench.
- Enhanced with capability checks and added NPU-P6 reference contract tests.
- Modified to include in the source list and refactor rejection logic.
- Updated README.md to document new test scripts and their purposes.
- Introduced differential tests for the APU-P7 frontend profile-1 BAM to ensure consistency with ROM and generator outputs.
- Implemented concurrent decode and continuous KWS smoke tests for APU-P7 to validate system stability under load.
- Added accuracy qualification tests for APU-P7 to verify through-hardware performance against expected results.
- Created contention tests for APU-P8 to assess USB2/SDIO0/APU Gateway A interactions.
- Developed quiesced loader admission tests for APU-P8 to ensure proper handling of DMA operations.
- Added post-fault visibility tests for APU-P8 HP interconnect to confirm fault handling capabilities.
- Enhanced register parity tests to include ABI digest verification for consistency across implementations.
- Updated publication register tests to reflect changes in capability constants for P5 and P7 profiles.
- Removed unsupported fault handling from and replaced it with a test for average pooling execution.
- Updated the test for unsupported placements to validate average pooling and depthwise convolution placements.
- Introduced new tests for softmax functionality in , including parameter validation and edge cases.
- Added qualification tests to ensure rejection of common-mode numerical errors and incomplete runs in .
- Enhanced RTL tests to cover memory downsizing and kernel burst capabilities in and .
- Adjusted boot status assertions in to reflect updated expected values.
- Introduced new CSRs for Hazard3 external interrupts in system_csr.h.
- Expanded the IRQ API in irq.h to include external IRQ enable/disable and priority setting functions.
- Implemented external IRQ handling in system_irq_handler.c, including registration, enabling, and dispatching.
- Created a new source file irq_nocsr.c for CSR-disabled firmware, providing stubs for external IRQ functions.
- Updated booter.c to reflect the new external IRQ count in printed specifications.
- Modified the soc_topology generation script to accommodate 64-bit IRQ vectors and external IRQ count.
- Enhanced the integration tests to validate the new IRQ handling and metadata generation.
- Adjusted various files to ensure compatibility with the new external IRQ architecture, including Verilog modules and test cases.
- Added new tests for FLAC encoding and decoding, including handling of rice parameters and partial LPC tail.
- Introduced WAV PCM encoding tests to ensure correct behavior across various configurations.
- Updated test cases to validate the handling of malformed FLAC files and metadata structures.
- Enhanced the APU register tests to include expanded P5 profile capabilities and ensure accurate register descriptions.
- Improved assertions for manifest checks in the APU release tests to validate ABI and instruction counts.
- Refactored existing tests for clarity and maintainability, ensuring they align with the latest APU specifications.
- Modified the capability register value in apu_reg_tb.sv to 0x01bd.
- Simplified rejected write checks for the COMMAND register in apu_reg_tb.sv.
- Added backend build ID input to the ring scheduler testbench.
- Updated test cases in test_apu.py to include new codec transport and controller files.
- Created new test file test_apu_codec_transport.py for APU-P5 transport assembler and parser tests.
- Added codec profile and dependency tests in test_apu_codecs.py.
- Enhanced register parity tests to include P5 primitive mask.
- Improved script tools tests for file download functionality and dependency helpers.
- Modified test_apu_register_parity.py to reflect changes in P4 ISA definitions.
- Updated test_apu_register_parity.py to include new manifest entries for P4.
- Enhanced test_script_tools.py to include checks for APU primitives filelists.
- Added assertions for APU primitives in the formal filelists test to ensure proper scoping and inclusion.
- Updated axi4_async_bridge_tb.sv to include unilateral reset handling in the test.
- Enhanced axi4_target_guard_tb.sv with a new task for read beat normalization and additional read tests.
- Introduced hp_axi4_mux3_rr_tb.sv to test round-robin arbitration for multiple AXI4 interfaces.
- Expanded test_apu.py to include tests for APU stream router, DMA, ring scheduler, and integrated DMA/ring/backend functionality.
- Added new test cases for APU-P2 Gateway A round-robin fairness.
- Updated test_clock_reset_domains.py to include APU data crossing.
- Enhanced test_script_tools.py to scope formal filelists for APU and Gateway A.
- Introduced new task in for handling high-performance APU writes with access fault checks.
- Updated to support an expanded resource count, including ownership and IRQ routing for the new APU resource.
- Enhanced to validate IRQ expectations for the newly added APU resource.
- Created for directed verification of APU-P1 APB4 register shell and integrated IRQ ownership topology.
- Added to ensure synchronization between RTL and SDK register ABI.
- Modified to parameterize tests for product modes, improving flexibility in testing.
- Updated to reflect changes in APU memory mapping and ensure correct assertions.
- Enhanced to validate the complete IRQ and resource allocations for the APU.
- Introduced
etrosoc-mini-feature-design skill for researching and freezing new SoC/IP features.
- Added
etrosoc-mini-feature-implementation skill for preflight and implementation of approved phases.
- Created
etrosoc-mini-feature-review skill for diagnosing failures and reviewing feature compliance.
- Developed corresponding YAML configurations and evaluation tests for each skill.
- Included a specification template for IP documentation and updated CODEOWNERS for agent directory.
- Enhanced tests to validate skill metadata, evaluation completeness, and manual input contracts.
- Introduced target in Makefile to run fast-flash HP Linux userspace acceptance tests with a 7200-second simulation time limit.
- Updated documentation to describe the new fast-flash model and its usage in simulations.
- Implemented Verilator-specific XPI core and fast flash model to handle slot-0 read operations with improved performance.
- Added new tests for the XPI fast flash model to verify protocol compliance and error handling.
- Enhanced existing tests to ensure proper integration of fast-flash features in the HP Linux simulation flow.
- Added TCD head and count registers to DMA definition and register files.
- Introduced CRC expected and result registers for enhanced error checking.
- Updated DMA version to 2.0 to reflect new features.
- Modified DMA testbench to validate new TCD and CRC functionalities.
- Enhanced README and filelists to include new dependencies and configurations.
- Updated formal verification and runtime tests to accommodate new DMA features.
- Updated axi4_interconnect_tb to include an additional master and issue high-priority access tests.
- Introduced hp_mailbox_tb for testing the HP mailbox functionality, including register and doorbell operations.
- Added plic_tb to validate PLIC priority, claim, and completion mechanisms.
- Enhanced pll_ctrl_tb to initialize additional system control signals.
- Updated soc_irq_topology_tb to account for new IRQ sources and validate IRQ signal behavior.
- Improved sysctrl_tb to include tests for HP lifecycle control and status registers.
- Added tests for HP boot bundle layout, CRC, and payload validation.
- Introduced test_hp_mailbox.py for RTL regression testing of the HP mailbox.
- Added test_hp_platform.py to validate HP platform configuration and generated-source boundaries.
- Enhanced test_librelane_flow.py to ensure correct signal placement in chip configuration.
- Added performance log tests to validate LP and HP coremark ratios.
- Updated test_soc_topology.py to reflect changes in IRQ and peripheral mappings.
- Updated to enforce stricter naming rules for new owned RTL.
- Expanded documentation on RTL coding style to include detailed naming contracts.
- Refactored RTL code to comply with new naming conventions, including:
- Renaming typedefs to use suffix for enums and for other types.
- Ensuring module names use lower snake case and ports have appropriate direction suffixes.
- Adjusting instance names to start with and ensuring state variables use and suffixes.
- Modified scripts to include checks for new naming rules and updated tests to validate these changes.
- Updated to reflect new naming guidelines and exceptions.
maksyuki