- Removed CORE and IP variables from common.tcl and synth.tcl scripts.
- Updated yosys.mk to exclude CORE and IP from environment variables.
- Modified bus_fault_tb to enhance NMI interface with management and user NMI signals.
- Added user access denial handling in bus_fault_tb.
- Updated pll_ctrl_tb and sysctrl_fault_tb to reflect changes in NMI interface.
- Adjusted test_gpio_user_mux.py to remove IP_MDD definition.
- Enhanced memory map tests to include user extensions and ensure proper generation.
- Updated test_script_tools.py to reflect changes in core management and user extensions.
- Refined topology tests to ensure user APB target is always added.
- Adjusted tech cell configuration tests to use simplified profile paths.
- Improved user extensions tests for scalar bindings and slot validation.
- Updated gen_iverilog_filelist.py to exclude sequential models from the file list for GF180 PDK.
- Introduced black box definitions for GF180 and SKY130 IO cells in their respective .sv files.
- Added simulation models for GF180 IO cells and sequential cells in gf180_seq_sim_cells.v.
- Modified tc_clk.sv to utilize specific clock cells for GF180 and SKY130 PDKs.
- Implemented bi-directional and tri-state pad modules for GF180 and SKY130 PDKs in tc_io.sv.
- Enhanced dependency lock validation to include submodule checks in dependency_lock.py.
- Updated setup_helpers.py to support selective submodule initialization.
- Created a comprehensive testbench for PDK cells in tc_pdk_cells_tb.sv.
- Added tests for dependency helper functions and tech cell configurations to ensure proper error handling.
maksyuki