- Added interface to and implemented error handling for register writes.
- Introduced a new test for AXI4 address gate functionality in .
- Updated clock and reset domain assertions in to reflect new domain names.
- Modified expected outputs in to include new clock domains.
- Adjusted chip configuration assertions in to account for additional power pads.
- Enhanced memory map tests in with new definitions and includes.
- Updated pin mapping tests in to include new reference clock pads.
- Improved script tools tests in to ensure correct validation of extension bindings.
- Refined system control tests in to include new clock control interface.
- Updated USB2 packet RAM tests in to include new SRAM definitions.
- Enhanced user extensions tests in to validate new product extension configurations.
- Adjusted user IP register parity tests to use legacy extensions.
- Updated Yosys synthesis recipe tests to reflect changes in STA period calculations.
- Introduced SYNTH_RECIPE variable to select between balanced, area, and speed synthesis recipes.
- Updated Makefile to handle new SYNTH_RECIPE variable and its validation.
- Modified synthesis scripts to utilize the selected recipe, ensuring outputs are directed to the appropriate directories.
- Enhanced documentation to reflect changes in synthesis flow and directory structure.
- Added tests to verify correct behavior of new synthesis recipes and their integration into the regression suite.
- Removed obsolete scripts and configurations related to previous synthesis methods.
maksyuki