Commit Graph
3 Commits
Author SHA1 Message Date
maksyuki fe347ed583 feat: add syn and floorplan design for librelane 2026-08-24 20:11:14 +08:00
maksyuki e7401c9390 feat: enhance LibreLane flow with safety features and update power rail connections 2026-08-24 09:09:15 +08:00
maksyuki 942ca936bf feat: Add IHP130 support and enhance power pin handling
- Updated filelist to include sg13g2_udp.v for IHP130.
- Modified sdram_axi4.sv to initialize read and write control signals.
- Enhanced clock and reset domain configuration to include jtag_trst_n_i_pad.
- Updated iverilog.mk to support IHP130 in tech-cell-test.
- Enhanced pin_map generation to include power pads for IHP130.
- Updated tc_io modules to handle power pins for IHP130.
- Added timing contract generation in package.py for commercial flow.
- Enhanced test cases to validate new IHP130 features and configurations.
- Added new tests for LibreLane flow specific to IHP130.
2026-08-23 22:27:04 +08:00