maksyuki
f633159109
- Clarified integration details for WS2812 and XPI in respective documentation. - Updated the SOC family positioning to reflect changes in clock/reset configurations and DMA channels. - Enhanced README files for librelane and RTL to include R2 target specifics, including execution order and peripheral contracts. - Specified the active execution order for R2 and clarified the implications of the new architecture on performance and integration.
3.9 KiB
IP Documentation
This directory owns architecture, register ABI, software contract, and verification documentation for self-owned retroSoC peripheral IP and platform extension interfaces.
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Tiny Gen1 QFN64 R2 freezes dual CPU I/D paths, four independent 32 KiB main-SRAM groups at the CPU's SYS frequency, per-target AXI32 concurrency and eight-channel DMA scheduling while preserving the package/pad budget and shared-IP ABIs. XPI retains MEM; Crypto retains PCLK. DVP V2 and optional NSS1 PSRAM remain the camera target. The active sequence is
TINY-R2-P0throughTINY-R2-P11; legacyTINY-P0throughTINY-P12remain in the linked contract history. The current 24 MHz/four-channel implementation and its evidence remain explicitly separate. -
timer.md defines the dual APB4 general timer.
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sysctrl.md defines the APB4 SystemCtrl register ABI, control-plane contracts, HAL, and verification.
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resource-controller.md defines root-managed resource ownership, IRQ routing, and cache-maintenance handoff.
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fabric-monitor.md defines data-plane counters, sticky fault retention, snapshot semantics, and the public HAL.
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user-ip.md defines the selectable user-IP window and software ownership boundary.
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ws2812.md defines the WS2812 transmitter.
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clint.md defines the management-hart software and timer interrupt block.
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gpio.md defines the dual-window GPIO controller.
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uart.md defines the APB4 UART controller.
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i2c.md defines the dual APB4 I2C controllers.
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dvp.md defines the APB4 DVP capture controller.
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i2s.md defines the APB4 I2S master transceiver.
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usb2.md defines the dual-role ULPI USB 2.0 controller, AXI4 descriptor DMA, dedicated-pad integration, HAL, and commercial release gates.
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crypto.md defines AES/SHA-2/RSA and its macro-first refreeze: six private SRAM banks, LP constant initialization, APB V2, bounded erasure, preserved algorithm/DMA/IRQ contracts and stable CRYPTO-P0/P1/P2 phases. The storage refreeze is specified, not yet implemented or qualified.
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jpeg.md defines the Baseline JPEG encoder/decoder, commercial reference survey, APB4/AXI4 DMA and SG-ring ABI, HAL, verification evidence, measured performance baseline, and 1080p60 optimization gates.
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ga2d.md freezes the Mini 2D graphics accelerator, private AXI64 DMA, APB4 and HAL ABI, expanded LP interrupts, ninth data master, and ordered implementation/evidence phases; it does not claim implemented RTL.
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apu.md defines the coreless Mini Audio Processing Unit, bounded codec microcode ISA, WAV/MP3/FLAC decode, private AXI4 DMA, APB4/ring ABI, I2S streams, independent KWS, lifecycle, and commercial delivery gates.
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npu.md freezes the independent 64-MAC, 64 KiB Mini NPU, private AXI64 DMA, APB4/job/HAL ABI, resource/IRQ and lifecycle contracts, and stable Phases 0-6. npu-verification.md defines numerical, fixed-model, protocol, performance and physical acceptance; implementation and evidence remain pending.
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mini-npu.md retains historical commercial NPU research; its old platform assumptions and architecture direction are superseded.
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sdram.md defines the AXI4 SDRAM data controller and APB4 configuration window.
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onchip-sram.md defines the shared SRAM ABI and technology boundary, with a separate integration note for Tiny R2's planned bank groups.
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xpi.md defines the native-AXI4/APB4 XPI V2 controller, commercial reference survey, LUT and PHY contracts, HAL, JTAG NOR programming, and delivery boundary.
The corresponding RTL and HAL implementations remain the executable sources of truth. Update the affected document whenever an IP interface or register ABI changes.