mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
0077546d6b
- Added burst handling to the AXI42RAM and AXI42RIBP modules, including support for fixed, increment, and wrap burst types. - Introduced address generation logic for read and write operations based on burst parameters. - Updated the AXI4 interconnect to validate burst types and lengths, ensuring compatibility with the AXI4 protocol. - Modified the SDRAM controller and testbench to accommodate the new burst handling features. - Enhanced test cases to verify the correct behavior of burst transactions and address patterns. - Adjusted memory map and topology tests to reflect changes in the SDRAM size and interface connections.
115 lines
3.7 KiB
Python
115 lines
3.7 KiB
Python
"""Directed tests for the active AXI4 fabric adapters."""
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from __future__ import annotations
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import os
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import shutil
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import subprocess
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import sys
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from pathlib import Path
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ROOT = Path(__file__).resolve().parents[1]
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def test_axi42ribp_supports_bursts_backpressure_and_errors(tmp_path: Path) -> None:
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verilator = shutil.which("verilator")
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if verilator is None:
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return
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output = tmp_path / "axi42ribp_burst_tb"
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ccache_tmp = tmp_path / "ccache"
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ccache_tmp.mkdir()
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subprocess.run(
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[
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verilator,
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"--binary",
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"--timing",
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"-Wno-fatal",
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"--top-module",
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"axi42ribp_burst_tb",
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"-I" + str(ROOT / "rtl/managed/clusterip/common/rtl"),
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"-I" + str(ROOT / "rtl/managed/clusterip/common/rtl/interface"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/interface/axi4_if.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ribp_if.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/interface/axi4_addr_gen.sv"),
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str(ROOT / "rtl/mini/top/axi42ribp_burst.sv"),
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str(ROOT / "tests/rtl/axi42ribp_burst_tb.sv"),
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"-Mdir",
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str(tmp_path / "obj"),
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"-o",
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str(output),
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],
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check=True,
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text=True,
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capture_output=True,
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env={
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**os.environ,
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"CCACHE_DIR": str(ccache_tmp),
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"CCACHE_TEMPDIR": str(ccache_tmp),
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},
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)
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result = subprocess.run([output], check=True, text=True, capture_output=True)
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assert "AXI4 to RIBP burst bridge test passed" in result.stdout
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def test_axi4_interconnect_classifies_decode_protocol_and_access_errors(
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tmp_path: Path,
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) -> None:
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verilator = shutil.which("verilator")
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if verilator is None:
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return
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memory_map = tmp_path / "memory_map"
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subprocess.run(
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[
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sys.executable,
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str(ROOT / "rtl/mini/address_map/generate_memory_map.py"),
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"--map",
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str(ROOT / "rtl/mini/address_map/memory_map.json"),
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"--output-dir",
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str(memory_map),
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"--have-sram-if",
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"NO",
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],
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check=True,
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)
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output = tmp_path / "axi4_interconnect_tb"
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ccache_tmp = tmp_path / "ccache"
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ccache_tmp.mkdir()
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subprocess.run(
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[
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verilator,
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"--binary",
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"--timing",
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"-Wno-fatal",
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"--top-module",
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"axi4_interconnect_tb",
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"-I" + str(memory_map / "rtl"),
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"-I" + str(ROOT / "rtl/mini/top"),
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"-I" + str(ROOT / "rtl/managed/clusterip/common/rtl"),
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"-I" + str(ROOT / "rtl/managed/clusterip/common/rtl/interface"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/interface/axi4_if.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/stream/round_robin_arbiter.sv"),
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str(ROOT / "rtl/mini/top/axi4_interconnect.sv"),
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str(ROOT / "rtl/mini/top/axi4_error_slave.sv"),
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str(ROOT / "tests/rtl/axi4_interconnect_tb.sv"),
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"-Mdir",
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str(tmp_path / "obj"),
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"-o",
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str(output),
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],
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check=True,
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text=True,
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capture_output=True,
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env={
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**os.environ,
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"CCACHE_DIR": str(ccache_tmp),
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"CCACHE_TEMPDIR": str(ccache_tmp),
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},
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)
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result = subprocess.run([output], check=True, text=True, capture_output=True)
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assert "AXI4 interconnect fault classification test passed" in result.stdout
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