mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
9c706ba0ff
- Updated paths in test files to reflect new directory structure for RTL and script files. - Changed references from rtl/mini to rtl/ip and scripts/rtl where applicable. - Added a new test file for Tiny product isolation, ensuring independent ABI and bus acceptance. - Enhanced tests for memory map generation and protocol contracts for Tiny architecture. - Ensured that all tests are aligned with the latest directory structure and naming conventions.
323 lines
9.6 KiB
Python
323 lines
9.6 KiB
Python
"""Focused standalone SDIO RTL regressions."""
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from __future__ import annotations
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import shutil
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import subprocess
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from pathlib import Path
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ROOT = Path(__file__).resolve().parents[1]
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CONVERTER = ROOT / "scripts/rtl/convt_sv2v.py"
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BUILD = ROOT / "build/test-sdio"
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SDIO_FULL_SOURCES = [
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"rtl/managed/clusterip/common/rtl/interface/apb4_if.sv",
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"rtl/managed/clusterip/common/rtl/interface/axi4_if.sv",
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"rtl/ip/storage/sdio_if.sv",
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"rtl/ip/storage/sdio_pkg.sv",
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"rtl/ip/storage/sdio_define.svh",
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"rtl/ip/storage/sdio_crc7.sv",
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"rtl/ip/storage/sdio_crc16.sv",
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"rtl/ip/storage/sdio_clock.sv",
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"rtl/ip/storage/sdio_command.sv",
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"rtl/ip/storage/sdio_data.sv",
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"rtl/ip/storage/sdio_dma_descriptor.sv",
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"rtl/ip/peripheral/dma_axi4_master.sv",
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"rtl/ip/storage/sdio_dma.sv",
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"rtl/ip/storage/sdio_reg.sv",
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"rtl/ip/storage/sdio_core.sv",
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"rtl/ip/storage/apb4_sdio.sv",
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"tests/rtl/sdio_native_model.sv",
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"tests/rtl/sdio_axi_memory_responder.sv",
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]
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SDIO_FULL_INCDIRS = [
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"rtl/managed/clusterip/common/rtl/interface",
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"rtl/ip/peripheral",
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"rtl/ip/storage",
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]
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def _run_tb(name: str, top: str, sources: list[str], incdirs: list[str], marker: str) -> None:
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iverilog = shutil.which("iverilog")
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vvp = shutil.which("vvp")
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if iverilog is None or vvp is None:
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return
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BUILD.mkdir(parents=True, exist_ok=True)
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filelist = BUILD / f"{name}.fl"
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filelist.write_text(
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"\n".join([*(f"+incdir+{ROOT / path}" for path in incdirs), *(str(ROOT / path) for path in sources)])
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+ "\n",
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encoding="utf-8",
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)
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converted = BUILD / f"{name}.v"
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simulation = BUILD / f"{name}.vvp"
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subprocess.run(
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["python3", str(CONVERTER), "-f", str(filelist), "--output", str(converted)],
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check=True,
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)
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subprocess.run([iverilog, "-g2012", "-s", top, "-o", str(simulation), str(converted)], check=True)
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result = subprocess.run([vvp, str(simulation)], check=True, text=True, capture_output=True)
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assert marker in result.stdout
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def _run_verilator_tb(
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name: str, top: str, sources: list[str], incdirs: list[str], marker: str
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) -> None:
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verilator = shutil.which("verilator")
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if verilator is None:
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return
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build_dir = BUILD / f"{name}-verilator"
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obj_dir = build_dir / "obj"
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obj_dir.mkdir(parents=True, exist_ok=True)
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source_paths = [str(ROOT / path) for path in sources]
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include_args = [f"-I{ROOT / path}" for path in incdirs]
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subprocess.run(
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[
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verilator,
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"--binary",
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"--timing",
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"--top-module",
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top,
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"-Mdir",
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str(obj_dir),
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"-o",
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"simv",
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*include_args,
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*source_paths,
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],
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check=True,
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)
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result = subprocess.run(
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[str(obj_dir / "simv")], check=True, text=True, capture_output=True
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)
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assert marker in result.stdout
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def test_sdio_crc_vectors() -> None:
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_run_tb(
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"crc",
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"sdio_crc_tb",
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[
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"rtl/ip/storage/sdio_pkg.sv",
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"rtl/ip/storage/sdio_crc7.sv",
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"rtl/ip/storage/sdio_crc16.sv",
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"tests/rtl/sdio_crc_tb.sv",
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],
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["rtl/ip/storage"],
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"SDIO CRC vectors passed",
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)
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def test_sdio_phase_clock() -> None:
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_run_tb(
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"clock",
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"sdio_clock_tb",
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["rtl/ip/storage/sdio_clock.sv", "tests/rtl/sdio_clock_tb.sv"],
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[],
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"SDIO phase clock test passed",
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)
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def test_sdio_command_engine() -> None:
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_run_tb(
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"command",
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"sdio_command_tb",
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[
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"rtl/ip/storage/sdio_pkg.sv",
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"rtl/ip/storage/sdio_clock.sv",
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"rtl/ip/storage/sdio_command.sv",
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"tests/rtl/sdio_command_tb.sv",
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],
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["rtl/ip/storage"],
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"SDIO command engine test passed",
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)
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def test_sdio_registers() -> None:
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_run_tb(
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"register",
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"sdio_register_tb",
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[
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"rtl/managed/clusterip/common/rtl/interface/apb4_if.sv",
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"rtl/ip/storage/sdio_pkg.sv",
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"rtl/ip/storage/sdio_define.svh",
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"rtl/ip/storage/sdio_reg.sv",
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"tests/rtl/sdio_register_tb.sv",
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],
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["rtl/managed/clusterip/common/rtl/interface", "rtl/ip/storage"],
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"SDIO APB register test passed",
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)
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def test_sdio_descriptors() -> None:
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_run_tb(
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"descriptor",
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"sdio_descriptor_tb",
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[
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"rtl/ip/storage/sdio_pkg.sv",
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"rtl/ip/storage/sdio_dma_descriptor.sv",
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"tests/rtl/sdio_descriptor_tb.sv",
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],
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["rtl/ip/storage"],
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"SDIO descriptor validation test passed",
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)
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def test_sdio_dma() -> None:
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_run_tb(
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"dma",
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"sdio_dma_tb",
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[
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"rtl/managed/clusterip/common/rtl/interface/axi4_if.sv",
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"rtl/ip/peripheral/dma_axi4_master.sv",
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"rtl/ip/storage/sdio_pkg.sv",
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"rtl/ip/storage/sdio_dma.sv",
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"tests/rtl/sdio_dma_tb.sv",
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],
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[
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"rtl/managed/clusterip/common/rtl/interface",
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"rtl/ip/peripheral",
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"rtl/ip/storage",
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],
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"SDIO DMA descriptor, tail, and 4 KiB split test passed",
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)
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def test_sdio_wrapper() -> None:
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_run_tb(
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"wrapper",
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"sdio_wrapper_tb",
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[
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"rtl/managed/clusterip/common/rtl/interface/apb4_if.sv",
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"rtl/managed/clusterip/common/rtl/interface/axi4_if.sv",
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"rtl/ip/storage/sdio_if.sv",
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"rtl/ip/storage/sdio_pkg.sv",
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"rtl/ip/storage/sdio_define.svh",
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"rtl/ip/storage/sdio_crc7.sv",
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"rtl/ip/storage/sdio_crc16.sv",
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"rtl/ip/storage/sdio_clock.sv",
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"rtl/ip/storage/sdio_command.sv",
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"rtl/ip/storage/sdio_data.sv",
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"rtl/ip/storage/sdio_dma_descriptor.sv",
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"rtl/ip/peripheral/dma_axi4_master.sv",
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"rtl/ip/storage/sdio_dma.sv",
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"rtl/ip/storage/sdio_reg.sv",
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"rtl/ip/storage/sdio_core.sv",
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"rtl/ip/storage/apb4_sdio.sv",
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"tests/rtl/sdio_wrapper_tb.sv",
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],
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[
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"rtl/managed/clusterip/common/rtl/interface",
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"rtl/ip/peripheral",
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"rtl/ip/storage",
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],
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"SDIO wrapper elaboration and APB smoke test passed",
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)
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def test_sdio_standalone_sdhc() -> None:
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_run_tb(
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"standalone-sdhc",
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"sdio_standalone_tb",
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[*SDIO_FULL_SOURCES, "tests/rtl/sdio_standalone_tb.sv"],
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SDIO_FULL_INCDIRS,
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"SDIO standalone native SD model test passed (SDHC)",
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)
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def test_sdio_standalone_sdsc() -> None:
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_run_tb(
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"standalone-sdsc",
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"sdio_sdsc_tb",
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[*SDIO_FULL_SOURCES, "tests/rtl/sdio_standalone_tb.sv"],
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SDIO_FULL_INCDIRS,
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"SDIO standalone native SD model test passed (SDSC)",
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)
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def test_sdio_standalone_onebit() -> None:
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_run_tb(
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"standalone-onebit",
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"sdio_onebit_tb",
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[*SDIO_FULL_SOURCES, "tests/rtl/sdio_standalone_tb.sv"],
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SDIO_FULL_INCDIRS,
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"SDIO standalone native SD model test passed (SDHC)",
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)
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def test_sdio_only_device() -> None:
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_run_tb(
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"sdio-only",
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"sdio_sdio_tb",
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[*SDIO_FULL_SOURCES, "tests/rtl/sdio_sdio_tb.sv"],
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SDIO_FULL_INCDIRS,
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"SDIO-only CMD5/CMD52/CMD53/DAT1 test passed",
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)
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def test_sdio_dual_instance() -> None:
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_run_tb(
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"dual",
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"sdio_dual_tb",
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[*SDIO_FULL_SOURCES, "tests/rtl/sdio_dual_tb.sv"],
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SDIO_FULL_INCDIRS,
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"SDIO dual-instance isolation and concurrent traffic test passed",
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)
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def test_sdio_dma_stress_contract() -> None:
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_run_tb(
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"dma-stress",
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"sdio_dma_stress_tb",
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[
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"rtl/managed/clusterip/common/rtl/interface/axi4_if.sv",
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"rtl/ip/peripheral/dma_axi4_master.sv",
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"rtl/ip/storage/sdio_pkg.sv",
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"rtl/ip/storage/sdio_dma.sv",
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"tests/rtl/sdio_axi_memory_responder.sv",
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"tests/rtl/sdio_dma_stress_tb.sv",
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],
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["rtl/managed/clusterip/common/rtl/interface", "rtl/ip/peripheral", "rtl/ip/storage"],
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"SDIO AXI 16-beat, 4 KiB split, error, and abort test passed",
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)
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def test_sdio_50mhz_clock() -> None:
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_run_tb(
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"50mhz",
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"sdio_50mhz_tb",
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["rtl/ip/storage/sdio_clock.sv", "tests/rtl/sdio_50mhz_tb.sv"],
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[],
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"SDIO 100 MHz to 50 MHz SDCLK test passed",
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)
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def test_sdio_50mhz_clock_verilator() -> None:
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_run_verilator_tb(
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"50mhz",
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"sdio_50mhz_tb",
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["rtl/ip/storage/sdio_clock.sv", "tests/rtl/sdio_50mhz_tb.sv"],
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[],
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"SDIO 100 MHz to 50 MHz SDCLK test passed",
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)
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def test_sdio_sdk_high_speed_enable_sequence() -> None:
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"""Keep the SDK high-speed capability/enable/verify/clock order explicit."""
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source = (ROOT / "crt/src/hal/sdio.c").read_text(encoding="utf-8")
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start = source.index("rs_sdio_function_initialize")
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end = source.index("rs_sdio_function_enable", start)
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initialize = source[start:end]
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capability_read = initialize.index('rs_sdio_function_cmd52_read(instance, 0U, 0x13U')
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enable_write = initialize.index("rs_sdio_function_cmd52_write", capability_read)
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verify_read = initialize.index('rs_sdio_function_cmd52_read(instance, 0U, 0x13U', enable_write)
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clock_change = initialize.index("rs_sdio_clock_set", verify_read)
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assert capability_read < enable_write < verify_read < clock_change
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assert "value | UINT8_C(0x02)" in initialize
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assert "value & UINT8_C(0x02)" in initialize
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high_speed_info = initialize.index("info->high_speed = high_speed_enabled")
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assert clock_change < high_speed_info
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