mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
9c706ba0ff
- Updated paths in test files to reflect new directory structure for RTL and script files. - Changed references from rtl/mini to rtl/ip and scripts/rtl where applicable. - Added a new test file for Tiny product isolation, ensuring independent ABI and bus acceptance. - Enhanced tests for memory map generation and protocol contracts for Tiny architecture. - Ensured that all tests are aligned with the latest directory structure and naming conventions.
90 lines
2.7 KiB
Python
90 lines
2.7 KiB
Python
"""RTL test for the direct RIB-to-APB bridge."""
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from __future__ import annotations
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import shutil
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import subprocess
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import sys
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from pathlib import Path
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ROOT = Path(__file__).resolve().parents[1]
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def test_rib2apb_preserves_apb_and_rib_handshakes(tmp_path: Path) -> None:
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iverilog = shutil.which("iverilog")
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sv2v = shutil.which("sv2v")
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vvp = shutil.which("vvp")
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if iverilog is None or sv2v is None or vvp is None:
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return
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memory_map = tmp_path / "memory_map"
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topology = tmp_path / "soc_topology"
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subprocess.run(
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[
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sys.executable,
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str(ROOT / "scripts/rtl/generate_memory_map.py"),
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"--map",
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str(ROOT / "rtl/mini/address_map/memory_map.json"),
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"--output-dir",
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str(memory_map),
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"--have-sram-if",
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"NO",
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],
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check=True,
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)
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subprocess.run(
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[
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sys.executable,
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str(ROOT / "rtl/mini/integration/generate_soc_topology.py"),
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"--map",
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str(ROOT / "rtl/mini/integration/soc_topology.json"),
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"--memory-map",
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str(ROOT / "rtl/mini/address_map/memory_map.json"),
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"--output-dir",
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str(topology),
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],
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check=True,
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)
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source_list = tmp_path / "rib2apb.fl"
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source_list.write_text(
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"\n".join(
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[
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"+define+SV_ASSRT_DISABLE",
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f"+incdir+{memory_map / 'rtl'}",
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f"+incdir+{topology / 'rtl'}",
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f"+incdir+{ROOT / 'rtl/mini/top'}",
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f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
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str(ROOT / "rtl/managed/clusterip/common/rtl/interface/apb4_pure_if.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/utils/spill_register.sv"),
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str(ROOT / "rtl/mini/top/rib_if.sv"),
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str(ROOT / "rtl/mini/top/rib2apb.sv"),
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str(ROOT / "tests/rtl/rib2apb_tb.sv"),
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"",
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]
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),
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encoding="utf-8",
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)
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converted = tmp_path / "rib2apb_tb.v"
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subprocess.run(
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[
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sys.executable,
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str(ROOT / "scripts/rtl/convt_sv2v.py"),
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"-f",
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str(source_list),
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"--output",
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str(converted),
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],
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check=True,
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)
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simulation = tmp_path / "rib2apb_tb"
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subprocess.run(
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[iverilog, "-g2012", "-s", "rib2apb_tb", "-o", str(simulation), str(converted)],
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check=True,
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)
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result = subprocess.run([vvp, str(simulation)], text=True, capture_output=True, check=True)
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assert "RIB2APB direct bridge test passed" in result.stdout
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