mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
068c05bf66
- Introduced PWM V2 alternate functions in the documentation, detailing the GPIO mappings and fault handling. - Updated the filelist to include new PWM RTL files for the PWM V2 implementation. - Modified the SOC topology JSON to reflect new GPIO alternate functions for PWM, including synchronization and capture inputs. - Updated software makefile to include PWM source and header files. - Enhanced the APB wrapper to integrate the PWM module with proper parameters. - Updated the ASIC top-level module to include new GPIO mappings for PWM functionality. - Added tests to validate the new GPIO and PWM connections in the topology.
221 lines
6.7 KiB
Systemverilog
221 lines
6.7 KiB
Systemverilog
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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`include "mmap_define.svh"
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`include "uart_define.svh"
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`include "pwm_define.svh"
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`include "ps2_define.svh"
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`include "user_extensions.svh"
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`include "soc_irq_config.svh"
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`include "archinfo_integration_metadata.svh"
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module ip_apb_wrapper (
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// verilog_format: off
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input logic clk_i,
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input logic rst_n_i,
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input logic clk_aud_i,
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input logic rst_aud_n_i,
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input logic debug_halted_i,
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input logic tmr_capch_i,
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rib_if.slave rib,
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uart_if.dut uart,
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pwm_if.dut pwm,
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ps2_if.dut ps2,
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input logic [`USER_IPSEL_WIDTH-1:0] ip_sel_i,
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user_gpio_if.user_ip user_gpio,
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output logic rtc_wake_o,
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output logic wdg_reset_req_o,
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output logic [`SOC_IRQ_APB_WIDTH-1:0] irq_o
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// verilog_format: on
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);
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localparam logic [7:0] ARCHINFO_MGMT_HART_COUNT = 8'd1;
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localparam logic [7:0] ARCHINFO_USER_CORE_COUNT = `USER_CORE_COUNT;
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localparam logic [7:0] ARCHINFO_GPIO_COUNT = 8'd32;
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localparam logic [7:0] ARCHINFO_IRQ_COUNT = `SOC_IRQ_VECTOR_WIDTH;
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localparam logic [31:0] ARCHINFO_TOPOLOGY = {
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ARCHINFO_IRQ_COUNT, ARCHINFO_GPIO_COUNT, ARCHINFO_USER_CORE_COUNT, ARCHINFO_MGMT_HART_COUNT
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};
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`ifdef HAVE_PLL
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localparam logic ARCHINFO_HAVE_PLL = 1'b1;
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`else
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localparam logic ARCHINFO_HAVE_PLL = 1'b0;
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`endif
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`ifdef HAVE_SRAM_IF
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localparam logic ARCHINFO_HAVE_SRAM_IF = 1'b1;
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localparam logic [31:0] ARCHINFO_SRAM_BYTES = 32'd131_072;
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`else
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localparam logic ARCHINFO_HAVE_SRAM_IF = 1'b0;
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localparam logic [31:0] ARCHINFO_SRAM_BYTES = 32'd0;
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`endif
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`ifdef HAVE_SRAM_MACRO
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localparam logic ARCHINFO_HAVE_SRAM_MACRO = 1'b1;
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`else
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localparam logic ARCHINFO_HAVE_SRAM_MACRO = 1'b0;
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`endif
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localparam logic [31:0] ARCHINFO_FEATURES0 =
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32'h0000_FFF8 | {31'd0, ARCHINFO_HAVE_PLL} |
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({31'd0, ARCHINFO_HAVE_SRAM_IF} << 1) | ({31'd0, ARCHINFO_HAVE_SRAM_MACRO} << 2);
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logic s_rng_entropy_enable;
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logic s_rng_entropy_ready;
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logic s_rng_entropy_valid;
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logic [31:0] s_rng_entropy_data;
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logic s_rng_entropy_qualified;
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logic s_rng_entropy_fault;
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logic s_rng_irq;
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`ifdef PDK_IHP130
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localparam logic [31:0] ARCHINFO_TECHNOLOGY = 32'h0201_0082;
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`elsif PDK_GF180
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localparam logic [31:0] ARCHINFO_TECHNOLOGY = 32'h0202_00B4;
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`elsif PDK_SKY130
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localparam logic [31:0] ARCHINFO_TECHNOLOGY = 32'h0203_0082;
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`elsif PDK_ICS55
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localparam logic [31:0] ARCHINFO_TECHNOLOGY = 32'h0204_0037;
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`else
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localparam logic [31:0] ARCHINFO_TECHNOLOGY = 32'h0000_0000;
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`endif
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// Generated timed and pure scalar APB interfaces preserve FPGA compatibility.
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`include "soc_apb_interfaces.svh"
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// Low-frequency peripherals retain their dedicated interfaces.
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rtc_if u_rtc_if (
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.rtc_clk_i (clk_aud_i),
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.rtc_rst_n_i(rst_aud_n_i)
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);
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wdg_if u_wdg_if (
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.wdg_clk_i (clk_aud_i),
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.wdg_rst_n_i (rst_aud_n_i),
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.debug_halted_i(debug_halted_i)
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);
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tmr_if u_tmr_if (.exclk_i(clk_aud_i));
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assign u_tmr_if.capch_i = tmr_capch_i;
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`include "soc_apb_bridges.svh"
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// verilog_format: off
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apb4_archinfo #(
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.VENDOR_ID (32'h0000_0000),
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.SOC_REVISION (32'h0001_0000),
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.BUILD_ID (`ARCHINFO_INTEGRATION_BUILD_ID),
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.CONFIG_ID (`ARCHINFO_INTEGRATION_CONFIG_ID),
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.BUILD_STATUS (`ARCHINFO_INTEGRATION_BUILD_STATUS),
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.REFERENCE_CLOCK_HZ(`SOC_EXT_CLK_HZ),
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.SRAM_BYTES (ARCHINFO_SRAM_BYTES),
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.TOPOLOGY (ARCHINFO_TOPOLOGY),
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.FEATURES0 (ARCHINFO_FEATURES0),
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.TECHNOLOGY (ARCHINFO_TECHNOLOGY)
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) u_apb4_archinfo (
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.device_id_i (128'h0000_0000_0000_0000_0000_0000_0000_0000),
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.device_id_valid_i (1'b0),
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.device_id_read_enable_i(1'b0),
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.apb4 (u_archinfo_apb_if)
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);
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// verilog_format: on
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rng_deterministic_source u_rng_deterministic_source (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.enable_i (s_rng_entropy_enable),
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.ready_i (s_rng_entropy_ready),
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.valid_o (s_rng_entropy_valid),
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.data_o (s_rng_entropy_data),
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.qualified_o(s_rng_entropy_qualified),
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.fault_o (s_rng_entropy_fault)
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);
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apb4_rng #(
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.FIFO_DEPTH(8)
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) u_apb4_rng (
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.entropy_enable_o (s_rng_entropy_enable),
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.entropy_ready_o (s_rng_entropy_ready),
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.entropy_valid_i (s_rng_entropy_valid),
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.entropy_data_i (s_rng_entropy_data),
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.entropy_qualified_i(s_rng_entropy_qualified),
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.entropy_fault_i (s_rng_entropy_fault),
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.irq_o (s_rng_irq),
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.apb4 (u_rng_apb_if)
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);
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apb4_uart #(
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.FIFO_DEPTH(32)
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) u_apb4_uart (
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.apb4(u_uart1_apb_if),
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.uart(uart)
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);
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apb4_pwm #(
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.PCLK_HZ(`SOC_EXT_CLK_HZ)
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) u_apb4_pwm (
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.debug_halted_i(debug_halted_i),
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.apb4 (u_pwm_apb_if),
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.pwm (pwm)
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);
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apb4_ps2 #(
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.PCLK_HZ (`SOC_EXT_CLK_HZ),
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.RX_FIFO_DEPTH(16),
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.TX_FIFO_DEPTH(16)
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) u_apb4_ps2 (
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.apb4(u_ps2_apb_if),
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.ps2 (ps2)
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);
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apb4_rtc #(
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.RTC_CLOCK_HZ(`SOC_AUD_CLK_HZ)
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) u_apb4_rtc (
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.apb4(u_rtc_apb_if),
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.rtc (u_rtc_if)
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);
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assign rtc_wake_o = u_rtc_if.wake_o;
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apb4_wdg #(
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.WDG_CLOCK_HZ (`SOC_AUD_CLK_HZ),
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.RESET_PULSE_CYCLES(8)
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) u_apb4_wdg (
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.apb4(u_wdg_apb_if),
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.wdg (u_wdg_if)
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);
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assign wdg_reset_req_o = u_wdg_if.reset_req_o;
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apb4_crc u_apb4_crc (.apb4(u_crc_apb_if));
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apb4_tmr u_apb4_tmr (
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.apb4(u_tmr_apb_if),
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.tmr (u_tmr_if)
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);
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// Generated IRQ ownership and core-vector bit assignments are topology checked.
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`include "soc_apb_irq_bindings.svh"
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rib2apb u_rib2apb (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.rib (rib),
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`include "soc_apb_connections.svh"
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);
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user_ip_wrapper u_user_ip_wrapper (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.sel_i (ip_sel_i),
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.gpio (user_gpio),
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.apb (u_user_ip_apb_if)
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);
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endmodule
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