mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
c9a3d7934c
- Introduced signal in sysctrl interface and module to handle RTC wake events. - Added RTC wake status register in memory map and updated related tests. - Integrated RTC wake handling in the APB wrapper and core wrapper. - Enhanced clock and reset domain configurations to include RTC signals. - Updated software build configurations to include RTC source files and headers. - Modified formal verification and testbench files to accommodate RTC wake functionality. - Ensured proper synchronization and status recording for RTC wake events in the sysctrl module.
339 lines
13 KiB
Python
339 lines
13 KiB
Python
"""Tests for the canonical Mini SoC address-map generator."""
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from __future__ import annotations
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import json
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import shutil
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import subprocess
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import sys
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from pathlib import Path
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ROOT = Path(__file__).resolve().parents[1]
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GENERATOR = ROOT / "rtl/mini/address_map/generate_memory_map.py"
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MEMORY_MAP = ROOT / "rtl/mini/address_map/memory_map.json"
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USER_EXTENSIONS = ROOT / "rtl/mini/integration/user_extensions.json"
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USER_GENERATOR = ROOT / "rtl/mini/integration/generate_user_extensions.py"
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def generate(output_dir: Path, *, sram: str = "NO") -> None:
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subprocess.run(
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[
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sys.executable,
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str(GENERATOR),
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"--map",
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str(MEMORY_MAP),
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"--output-dir",
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str(output_dir),
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"--have-sram-if",
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sram,
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],
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check=True,
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)
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subprocess.run(
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[
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sys.executable,
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str(USER_GENERATOR),
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"--map",
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str(USER_EXTENSIONS),
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"--output-dir",
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str(output_dir / "user_extensions"),
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],
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check=True,
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)
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def test_generated_artifacts_share_the_capacity_baseline(tmp_path: Path) -> None:
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generate(tmp_path, sram="YES")
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rtl = (tmp_path / "rtl/mmap_define.svh").read_text(encoding="utf-8")
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header = (tmp_path / "include/retrosoc/generated/memory_map.h").read_text(encoding="utf-8")
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linker = (tmp_path / "linker/memory_regions.ld").read_text(encoding="utf-8")
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assert "`define SOC_ADDR_PSRAM_END 32'h407FFFFF" in rtl
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assert "`define SOC_ADDR_XPI_END 32'h5FFFFFFF" in rtl
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assert "`define SOC_ADDR_IS_FLASH(addr) ((addr) <= `SOC_ADDR_FLASH_END)" in rtl
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assert "`define CPU_RESET_ADDR `SOC_CPU_RESET_ADDR" in rtl
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assert "`define SOC_ADDR_IS_RESERVED(addr)" in rtl
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assert "RS_SOC_PSRAM_SIZE UINT32_C(0x00800000)" in header
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assert "RS_SOC_SDRAM_SIZE UINT32_C(0x02000000)" in header
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assert "RS_SOC_SPISD_SIZE UINT32_C(0x40000000)" in header
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assert "#ifdef __ASSEMBLER__" in header
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assert "#define UINT32_C(value) value" in header
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assert "RS_SOC_RIBP_SDIO_BASE" not in header
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assert "RS_SOC_NMI_" not in header
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assert "RS_SOC_OPIPSRAM_BASE" not in header
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assert "RS_SOC_HAS_SRAM 1U" in header
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assert "SOC_SYSCTRL_PLL_CFG_OFFSET 32'h00000008" in rtl
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assert "SOC_SYSCTRL_PLL_STATUS_OFFSET 32'h0000001C" in rtl
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assert "SOC_SYSCTRL_TEST_STATUS_OFFSET 32'h00000084" in rtl
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assert "SOC_SYSCTRL_RTC_WAKE_STATUS_OFFSET 32'h00000088" in rtl
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assert "SOC_ADDR_IS_RIBP(addr)" in rtl
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assert "SOC_ADDR_IS_NMI" not in rtl
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user_policy = rtl.split("`define SOC_USER_ADDR_READABLE", 1)[1].split(
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"`define SOC_ADDR_INCR4_CAPABLE", 1
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)[0]
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assert "SOC_ADDR_IS_APB_RNG" not in user_policy
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assert "RS_SOC_SYSCTRL_PLL_CFG_OFFSET UINT32_C(0x00000008)" in header
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assert "RS_SOC_SYSCTRL_PLL_STATUS_OFFSET UINT32_C(0x0000001C)" in header
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assert "RS_SOC_SYSCTRL_TEST_STATUS_OFFSET UINT32_C(0x00000084)" in header
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assert "RS_SOC_SYSCTRL_RTC_WAKE_STATUS_OFFSET UINT32_C(0x00000088)" in header
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assert "PSRAM (wxa!ri) : ORIGIN = 0x40000000, LENGTH = 0x00800000" in linker
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def test_user_ip_is_always_emitted_for_the_fixed_platform(tmp_path: Path) -> None:
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generate(tmp_path)
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rtl = (tmp_path / "rtl/mmap_define.svh").read_text(encoding="utf-8")
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header = (tmp_path / "include/retrosoc/generated/memory_map.h").read_text(encoding="utf-8")
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assert "SOC_ADDR_APB_USER_IP_BASE" in rtl
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assert "RS_SOC_APB_USER_IP_BASE" in header
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def test_bootstrap_assembly_uses_the_generated_gpio_admin_base() -> None:
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for source in (ROOT / "crt/arch/riscv/startup.S", ROOT / "app/asm/hello.s"):
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text = source.read_text(encoding="utf-8")
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assert '#include "retrosoc/generated/memory_map.h"' in text
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assert "RS_SOC_RIBP_GPIO_ADMIN_BASE + 0x34" in text
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assert "RS_SOC_RIBP_GPIO_ADMIN_BASE + 0x38" in text
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assert "RS_SOC_RIBP_PSRAM_BASE + 0x08" in text
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assert "0x10000028" not in text
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assert "0x1000002c" not in text
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def test_map_validation_rejects_overlaps(tmp_path: Path) -> None:
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document = json.loads(MEMORY_MAP.read_text(encoding="utf-8"))
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document["regions"][1]["base"] = document["regions"][0]["base"]
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invalid_map = tmp_path / "overlap.json"
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invalid_map.write_text(json.dumps(document), encoding="utf-8")
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result = subprocess.run(
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[sys.executable, str(GENERATOR), "--map", str(invalid_map), "--check"],
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text=True,
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capture_output=True,
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)
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assert result.returncode != 0
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assert "address-map overlap" in result.stderr
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def test_bus_fault_responder_handles_reserved_and_unmapped_addresses(tmp_path: Path) -> None:
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iverilog = shutil.which("iverilog")
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vvp = shutil.which("vvp")
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if iverilog is None or vvp is None:
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return
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generate(tmp_path)
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simulation = tmp_path / "bus_fault_tb"
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source_list = tmp_path / "bus_fault.fl"
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source_list.write_text(
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"\n".join(
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[
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"+define+SV_ASSRT_DISABLE",
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f"+incdir+{tmp_path / 'rtl'}",
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f"+incdir+{tmp_path / 'user_extensions' / 'rtl'}",
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f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
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str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ribp_if.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ram_if.sv"),
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str(ROOT / "rtl/mini/top/rib_if.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/utils/spill_register.sv"),
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str(ROOT / "rtl/mini/top/ribp2rib.sv"),
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str(ROOT / "rtl/mini/top/rib2ribp.sv"),
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str(ROOT / "rtl/mini/top/rib_error_slave.sv"),
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str(ROOT / "rtl/mini/top/rib2ram.sv"),
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str(ROOT / "rtl/mini/top/bus.sv"),
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str(ROOT / "tests/rtl/bus_fault_tb.sv"),
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"",
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]
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),
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encoding="utf-8",
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)
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converted = tmp_path / "bus_fault_tb.v"
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subprocess.run(
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[
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sys.executable,
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str(ROOT / "rtl/mini/script/convt_sv2v.py"),
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"-f",
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str(source_list),
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"--output",
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str(converted),
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],
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check=True,
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)
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subprocess.run(
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[
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iverilog,
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"-g2012",
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"-s",
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"bus_fault_tb",
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"-o",
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str(simulation),
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str(converted),
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],
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check=True,
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)
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result = subprocess.run([vvp, str(simulation)], text=True, capture_output=True, check=True)
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assert "bus fault responder test passed" in result.stdout
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def test_sysctrl_fault_registers_record_and_clear_pending(tmp_path: Path) -> None:
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iverilog = shutil.which("iverilog")
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vvp = shutil.which("vvp")
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if iverilog is None or vvp is None:
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return
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generate(tmp_path)
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source_list = tmp_path / "sysctrl_fault.fl"
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source_list.write_text(
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"\n".join(
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[
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"+define+SV_ASSRT_DISABLE",
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f"+incdir+{tmp_path / 'rtl'}",
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f"+incdir+{tmp_path / 'user_extensions' / 'rtl'}",
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f"+incdir+{ROOT / 'rtl/mini/top'}",
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f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
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str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ribp_if.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/cdc/cdc_sync.sv"),
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str(ROOT / "rtl/ip/ribp/peripheral/pll_ctrl_if.sv"),
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str(ROOT / "rtl/ip/ribp/peripheral/sysctrl.sv"),
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str(ROOT / "tests/rtl/sysctrl_fault_tb.sv"),
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"",
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]
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),
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encoding="utf-8",
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)
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converted = tmp_path / "sysctrl_fault_tb.v"
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subprocess.run(
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[
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sys.executable,
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str(ROOT / "rtl/mini/script/convt_sv2v.py"),
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"-f",
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str(source_list),
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"--output",
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str(converted),
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],
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check=True,
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)
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simulation = tmp_path / "sysctrl_fault_tb"
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subprocess.run(
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[iverilog, "-g2012", "-s", "sysctrl_fault_tb", "-o", str(simulation), str(converted)],
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check=True,
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)
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result = subprocess.run([vvp, str(simulation)], text=True, capture_output=True, check=True)
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assert "sysctrl fault, user core control, and RTC wake test passed" in result.stdout
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def test_pll_controller_reconfigures_and_falls_back_to_the_safe_clock(tmp_path: Path) -> None:
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iverilog = shutil.which("iverilog")
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vvp = shutil.which("vvp")
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if iverilog is None or vvp is None:
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return
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generate(tmp_path)
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source_list = tmp_path / "pll_ctrl.fl"
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source_list.write_text(
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"\n".join(
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[
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"+define+SV_ASSRT_DISABLE",
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"+define+PDK_BEHAV",
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"+define+HAVE_PLL",
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f"+incdir+{tmp_path / 'rtl'}",
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f"+incdir+{tmp_path / 'user_extensions' / 'rtl'}",
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f"+incdir+{ROOT / 'rtl/mini/top'}",
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f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
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str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ribp_if.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/cdc/cdc_sync.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/cdc/cdc_rst_ctrlr.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/cdc/cdc_2phase.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/clkrst/rst_sync.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/clkrst/counter.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/utils/edge_det.sv"),
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str(ROOT / "rtl/ip/ribp/peripheral/pll_ctrl_if.sv"),
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str(ROOT / "rtl/ip/ribp/peripheral/clint_timebase.sv"),
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str(ROOT / "rtl/ip/ribp/peripheral/sysctrl.sv"),
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str(ROOT / "rtl/tech/tc_clk.sv"),
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str(ROOT / "rtl/tech/tc_pll.sv"),
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str(ROOT / "rtl/mini/top/rcu.sv"),
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str(ROOT / "tests/rtl/pll_ctrl_tb.sv"),
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"",
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]
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),
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encoding="utf-8",
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)
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converted = tmp_path / "pll_ctrl_tb.v"
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subprocess.run(
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[
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sys.executable,
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str(ROOT / "rtl/mini/script/convt_sv2v.py"),
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"-f",
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str(source_list),
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"--output",
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str(converted),
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],
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check=True,
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)
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simulation = tmp_path / "pll_ctrl_tb"
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subprocess.run(
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[iverilog, "-g2012", "-s", "pll_ctrl_tb", "-o", str(simulation), str(converted)],
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check=True,
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)
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result = subprocess.run([vvp, str(simulation)], text=True, capture_output=True, check=True)
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assert "pll controller dynamic configuration test passed" in result.stdout
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result = subprocess.run(
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[vvp, str(simulation), "+pll_lock_fail"], text=True, capture_output=True, check=True
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)
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assert "pll controller timeout test passed" in result.stdout
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unsupported_list = tmp_path / "pll_unsupported.fl"
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unsupported_list.write_text(
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source_list.read_text(encoding="utf-8").replace("+define+HAVE_PLL\n", ""),
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encoding="utf-8",
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)
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unsupported_converted = tmp_path / "pll_unsupported_tb.v"
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subprocess.run(
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[
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sys.executable,
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str(ROOT / "rtl/mini/script/convt_sv2v.py"),
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"-f",
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str(unsupported_list),
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"--output",
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str(unsupported_converted),
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],
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check=True,
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)
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unsupported_simulation = tmp_path / "pll_unsupported_tb"
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subprocess.run(
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[
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iverilog,
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"-g2012",
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"-s",
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"pll_ctrl_tb",
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"-o",
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str(unsupported_simulation),
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str(unsupported_converted),
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],
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check=True,
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)
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result = subprocess.run(
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[vvp, str(unsupported_simulation)], text=True, capture_output=True, check=True
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)
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assert "pll controller capability gate test passed" in result.stdout
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def test_sysctrl_does_not_expose_unused_i2c_or_qspi_select_registers() -> None:
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rtl = (ROOT / "rtl/ip/ribp/peripheral/sysctrl.sv").read_text(encoding="utf-8")
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header = (ROOT / "crt/include/retrosoc/core/soc.h").read_text(encoding="utf-8")
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for symbol in (
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"SYSCTRL_I2CSEL",
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"SYSCTRL_QSPISEL",
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"i2c_sel_o",
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"qspi_sel_o",
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"s_sysctrl_i2csel",
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"s_sysctrl_qspisel",
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):
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assert symbol not in rtl
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assert "reg_sysctrl_i2csel" not in header
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assert "reg_sysctrl_qspicsel" not in header
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