maksyuki 075344df58 feat: add SPI-SD RTL tests and enhance interconnect testbench ...

- Increased the number of masters in the AXI4 interconnect testbench from 5 to 6.
- Added new testbench for SPI-SD clock functionality (spisd_clock_tb).
- Introduced testbench for SPI-SD command engine (spisd_command_tb).
- Created testbench for SPI-SD CRC calculation (spisd_crc_tb).
- Implemented testbench for SPI-SD data handling (spisd_data_tb).
- Developed wrapper testbench for SPI-SD with APB and training checks (spisd_wrapper_tb).
- Added Python test suite for SPI-SD RTL regressions (test_spisd.py).
- Created a test for verifying register parity between RTL and C header definitions (test_spisd_register_parity.py).

2026-08-20 16:12:15 +08:00

..

test_runtime.c

feat: add SPI-SD RTL tests and enhance interconnect testbench

2026-08-20 16:12:15 +08:00