mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 22:55:14 +00:00
maksyuki
a87236ae33
- Renamed and to and respectively across various test files and modules. - Updated response codes in tests to use new definitions (). - Added new testbench to validate RIB to RAM interactions. - Created for testing RIBP topology routing. - Adjusted memory map tests to reflect new interface names. - Ensured all references to old interface names were replaced in Python test scripts. - Verified that all test cases pass with the new interface structure.
114 lines
3.2 KiB
Systemverilog
114 lines
3.2 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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module formal_apb_slave (
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apb4_pure_if.slave apb
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);
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(* anyseq *)logic f_ready;
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(* anyseq *)logic [31:0] f_rdata;
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(* anyseq *)logic f_slverr;
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assign apb.pready = f_ready;
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assign apb.prdata = f_rdata;
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assign apb.pslverr = f_slverr;
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endmodule
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module ribp2apb_formal_design (
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input logic clk_i,
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output logic rst_n_i,
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output logic f_past_valid,
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output logic rib_valid,
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output logic [31:0] rib_addr,
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output logic [31:0] rib_wdata,
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output logic [ 3:0] rib_wstrb,
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output logic rib_ready,
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output logic rib_resp_err,
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output logic [ 9:0] psel_comb,
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output logic [ 9:0] psel_q,
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output logic xfer_ready,
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output logic xfer_error,
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output logic [ 1:0] fsm_q
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);
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ribp_if rib ();
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apb4_pure_if archinfo ();
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apb4_pure_if rng ();
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apb4_pure_if uart ();
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apb4_pure_if pwm ();
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apb4_pure_if ps2 ();
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apb4_pure_if rtc ();
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apb4_pure_if wdg ();
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apb4_pure_if crc ();
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apb4_pure_if tmr ();
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apb4_pure_if user_ip ();
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(* anyseq *)logic f_rib_valid;
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(* anyseq *)logic [31:0] f_rib_addr;
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(* anyseq *)logic [31:0] f_rib_wdata;
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(* anyseq *)logic [ 3:0] f_rib_wstrb;
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assign rib.valid = f_rib_valid;
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assign rib.addr = f_rib_addr;
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assign rib.wdata = f_rib_wdata;
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assign rib.wstrb = f_rib_wstrb;
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assign rib_valid = rib.valid;
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assign rib_addr = rib.addr;
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assign rib_wdata = rib.wdata;
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assign rib_wstrb = rib.wstrb;
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assign rib_ready = rib.ready;
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assign rib_resp_err = rib.resp_err;
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formal_apb_slave u_archinfo_slave (.apb(archinfo));
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formal_apb_slave u_rng_slave (.apb(rng));
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formal_apb_slave u_uart_slave (.apb(uart));
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formal_apb_slave u_pwm_slave (.apb(pwm));
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formal_apb_slave u_ps2_slave (.apb(ps2));
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formal_apb_slave u_rtc_slave (.apb(rtc));
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formal_apb_slave u_wdg_slave (.apb(wdg));
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formal_apb_slave u_crc_slave (.apb(crc));
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formal_apb_slave u_tmr_slave (.apb(tmr));
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formal_apb_slave u_user_ip_slave (.apb(user_ip));
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ribp2apb u_dut (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.ribp (rib),
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.archinfo(archinfo),
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.rng (rng),
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.uart (uart),
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.pwm (pwm),
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.ps2 (ps2),
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.rtc (rtc),
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.wdg (wdg),
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.crc (crc),
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.tmr (tmr),
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.user_ip (user_ip)
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);
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assign psel_comb = u_dut.s_psel_comb;
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assign psel_q = u_dut.s_psel_q;
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assign xfer_ready = u_dut.s_xfer_ready;
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assign xfer_error = u_dut.s_xfer_error;
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assign fsm_q = u_dut.s_fsm_q;
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initial begin
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rst_n_i = 1'b0;
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f_past_valid = 1'b0;
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end
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always_ff @(posedge clk_i) begin
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rst_n_i <= 1'b1;
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f_past_valid <= 1'b1;
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end
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endmodule
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