maksyuki
0a6055134e
- Updated NMI interface references from to in multiple files for consistency. - Added a new script to convert UART performance records into structured JSON format. - Enhanced the README documentation to include details about the new performance log parser. - Implemented tests for the new performance log parser to ensure correct functionality. - Added new test cases for DMA error handling and SDRAM data integrity to improve coverage. - Updated existing test cases to accommodate changes in the NMI interface and added performance metrics. - Refactored bus fault testbench to include fault code checks and improved error handling. - Adjusted memory map generation and pin mapping tests to reflect recent changes in RTL structure.
1.0 KiB
RTL Design and Simulation
This directory contains retroSoC SystemVerilog RTL, CPU/IP integration, peripheral and technology wrappers, filelists, testbench support, and the Mini SoC build entry points.
mini/ is the active SoC integration flow. managed/ contains locked or
vendored integration inputs, while ip/ contains self-owned IP and
experiments. filelist/ selects PDK-specific RTL sources; tech/ contains
technology wrappers. Respect managed upstream boundaries and use setup helpers
rather than editing generated MPW output.
RTL changes require an affected firmware build and simulation. Use
make regress-pr or make regress-nightly for supported regression coverage;
see Engineering Workflow for results and artifacts.
The Verilator harness uses a zero-delay SDRAM protocol model because Verilator does not elaborate the tri-state delays in the Micron model. The Icarus testbench retains that Micron timing model, so it is the reference for SDRAM command timing while Verilator provides fast functional coverage.