mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
0a6055134e
- Updated NMI interface references from to in multiple files for consistency. - Added a new script to convert UART performance records into structured JSON format. - Enhanced the README documentation to include details about the new performance log parser. - Implemented tests for the new performance log parser to ensure correct functionality. - Added new test cases for DMA error handling and SDRAM data integrity to improve coverage. - Updated existing test cases to accommodate changes in the NMI interface and added performance metrics. - Refactored bus fault testbench to include fault code checks and improved error handling. - Adjusted memory map generation and pin mapping tests to reflect recent changes in RTL structure.
86 lines
2.4 KiB
Systemverilog
86 lines
2.4 KiB
Systemverilog
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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`include "mmap_define.svh"
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module nmi2apb (
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// verilog_format: off
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input logic clk_i,
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input logic rst_n_i,
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nmi_if.slave nmi,
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output logic resp_err_o,
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`include "soc_apb_ports.svh"
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// verilog_format: on
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);
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localparam FSM_IDLE = 2'd0;
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localparam FSM_SETP = 2'd1;
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localparam FSM_ENAB = 2'd2;
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logic [31:0] s_rd_data;
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logic s_xfer_valid, s_xfer_ready, s_xfer_error;
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logic s_mem_valid_re;
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logic [1:0] s_fsm_d, s_fsm_q;
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// Registered slave-select one-hot for response mux
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`include "soc_apb_declarations.svh"
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// Generated APB request routing retains the scalar interface protocol.
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`include "soc_apb_request_routes.svh"
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// verilog_format: off
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edge_det_sync_re #(1) u_mem_valid_edge_det_sync_re (
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clk_i,
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rst_n_i,
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nmi.valid,
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s_mem_valid_re
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);
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// verilog_format: on
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assign s_xfer_valid = ((s_fsm_q == FSM_IDLE) && s_mem_valid_re) ||
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(s_fsm_q == FSM_SETP) || (s_fsm_q == FSM_ENAB);
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always_comb begin
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s_fsm_d = s_fsm_q;
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unique case (s_fsm_q)
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FSM_IDLE: if (s_mem_valid_re) s_fsm_d = FSM_SETP;
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FSM_SETP: s_fsm_d = FSM_ENAB;
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FSM_ENAB: if (s_xfer_ready) s_fsm_d = FSM_IDLE;
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default: s_fsm_d = s_fsm_q;
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endcase
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end
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dffr #(2) u_fsm_dffr (
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clk_i,
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rst_n_i,
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s_fsm_d,
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s_fsm_q
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);
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assign nmi.ready = nmi.valid && (s_fsm_q == FSM_ENAB) && s_xfer_ready;
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assign nmi.rdata = {32{nmi.ready}} & s_rd_data;
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assign resp_err_o = nmi.ready && s_xfer_error;
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// Capture slave-select one-hot at FSM_SETP for cleaner response mux.
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`include "soc_apb_select_routes.svh"
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assign s_psel_d = (s_fsm_q == FSM_IDLE && s_mem_valid_re) ? s_psel_comb : s_psel_q;
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dffr #(NSLV) u_psel_dffr (
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clk_i,
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rst_n_i,
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s_psel_d,
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s_psel_q
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);
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// Generated response mux uses the registered one-hot target selection.
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`include "soc_apb_response_mux.svh"
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endmodule
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