mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
d886cd992c
- Updated the file to improve code readability and maintainability by removing commented-out code and adding generated GPIO alternate-function wiring. - Modified to streamline simulation command configurations and removed unnecessary variables. - Introduced a new testbench to validate NMI routing functionality within the SoC topology. - Added comprehensive tests in to ensure the correctness of generated bindings and validate topology constraints. - Adjusted to reflect changes in regression command imports and ensure uniform timeout settings for Verilator simulations.
113 lines
3.3 KiB
Systemverilog
113 lines
3.3 KiB
Systemverilog
`timescale 1ns / 1ps
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`include "mmap_define.svh"
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module soc_topology_nmi_tb;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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nmi_if nmi ();
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`include "soc_nmi_interfaces.svh"
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`include "soc_nmi_routes.svh"
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always #5 clk_i = ~clk_i;
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task automatic expect_route(input logic [31:0] address, input integer slot,
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input logic [31:0] expected_rdata);
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begin
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@(negedge clk_i);
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nmi.addr = address;
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nmi.valid = 1'b1;
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#1;
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if (s_slv_sel_d !== (18'd1 << slot)) begin
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$fatal(1, "unexpected target slot for %h", address);
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end
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@(posedge clk_i);
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#1;
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if (!nmi.ready || nmi.rdata !== expected_rdata) begin
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$fatal(1, "unexpected response for %h", address);
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end
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@(negedge clk_i);
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nmi.valid = 1'b0;
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@(posedge clk_i);
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end
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endtask
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task automatic expect_disabled(input logic [31:0] address);
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begin
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@(negedge clk_i);
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nmi.addr = address;
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nmi.valid = 1'b1;
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#1;
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if (s_slv_sel_d !== '0) begin
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$fatal(1, "disabled target accepted %h", address);
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end
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@(posedge clk_i);
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#1;
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if (nmi.ready || nmi.rdata !== '0) begin
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$fatal(1, "disabled target responded to %h", address);
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end
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@(negedge clk_i);
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nmi.valid = 1'b0;
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@(posedge clk_i);
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end
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endtask
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initial begin
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nmi.valid = 1'b0;
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nmi.addr = '0;
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nmi.wdata = '0;
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nmi.wstrb = '0;
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u_uart_nmi_if.ready = 1'b1;
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u_gpio_nmi_if.ready = 1'b1;
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u_tim0_nmi_if.ready = 1'b1;
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u_tim1_nmi_if.ready = 1'b1;
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u_psram_nmi_if.ready = 1'b1;
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u_spisd_nmi_if.ready = 1'b1;
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u_i2c0_nmi_if.ready = 1'b1;
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u_i2s_nmi_if.ready = 1'b1;
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u_onewire_nmi_if.ready = 1'b1;
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u_xpi_nmi_if.ready = 1'b1;
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u_dma_nmi_if.ready = 1'b1;
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u_sysctrl_nmi_if.ready = 1'b1;
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u_clint_nmi_if.ready = 1'b1;
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u_sdram_nmi_if.ready = 1'b1;
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u_dvp_nmi_if.ready = 1'b1;
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u_sdio_nmi_if.ready = 1'b1;
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u_opipsram_nmi_if.ready = 1'b1;
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u_i2c1_nmi_if.ready = 1'b1;
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u_uart_nmi_if.rdata = 32'h0000_0000;
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u_gpio_nmi_if.rdata = 32'h1111_1111;
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u_tim0_nmi_if.rdata = 32'h2222_2222;
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u_tim1_nmi_if.rdata = 32'h3333_3333;
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u_psram_nmi_if.rdata = 32'h4444_4444;
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u_spisd_nmi_if.rdata = 32'h5555_5555;
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u_i2c0_nmi_if.rdata = 32'h6666_6666;
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u_i2s_nmi_if.rdata = 32'h7777_7777;
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u_onewire_nmi_if.rdata = 32'h8888_8888;
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u_xpi_nmi_if.rdata = 32'h9999_9999;
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u_dma_nmi_if.rdata = 32'hAAAA_AAAA;
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u_sysctrl_nmi_if.rdata = 32'hBBBB_BBBB;
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u_clint_nmi_if.rdata = 32'hCCCC_CCCC;
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u_sdram_nmi_if.rdata = 32'hDDDD_DDDD;
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u_dvp_nmi_if.rdata = 32'hEEEE_EEEE;
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u_sdio_nmi_if.rdata = 32'hF0F0_F0F0;
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u_opipsram_nmi_if.rdata = 32'h0F0F_0F0F;
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u_i2c1_nmi_if.rdata = 32'h1234_5678;
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repeat (2) @(posedge clk_i);
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rst_n_i = 1'b1;
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expect_route(`SOC_ADDR_NMI_GPIO_BASE, 1, 32'h1111_1111);
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expect_route(`SOC_ADDR_PSRAM_BASE, 4, 32'h4444_4444);
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expect_route(`SOC_ADDR_FLASH_BASE, 9, 32'h9999_9999);
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expect_route(`SOC_ADDR_NMI_I2C1_BASE, 17, 32'h1234_5678);
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expect_disabled(`SOC_ADDR_NMI_SDIO_BASE);
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$display("SoC topology NMI routing test passed");
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$finish;
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end
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endmodule
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