mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
08ecc4aaea
- Updated the PSRAM register module to include additional signals for better control and data management. - Introduced dedicated signals for each register's data and enable lines, enhancing clarity and maintainability. - Replaced synchronous assignments with combinational logic for register updates. - Added new D flip-flops for various control signals to ensure proper synchronization. - Improved the performance control logic to reset counters based on specific conditions. - Minor formatting adjustments in the I2S register and APB4 I2S modules for consistency. - Updated test script to include additional utility files for comprehensive testing.
104 lines
3.5 KiB
Python
104 lines
3.5 KiB
Python
"""Directed tests for the ESP-PSRAM64H controller and its handwritten ABI."""
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from __future__ import annotations
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import os
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import re
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import shutil
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import subprocess
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import sys
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from pathlib import Path
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ROOT = Path(__file__).resolve().parents[1]
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def test_psram_controller_data_integrity_and_fault_isolation(tmp_path: Path) -> None:
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verilator = shutil.which("verilator")
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if verilator is None:
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return
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generated = tmp_path / "generated"
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subprocess.run(
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[
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sys.executable,
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str(ROOT / "rtl/mini/address_map/generate_memory_map.py"),
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"--map",
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str(ROOT / "rtl/mini/address_map/memory_map.json"),
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"--output-dir",
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str(generated),
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"--have-sram-if",
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"NO",
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],
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check=True,
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)
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output = tmp_path / "psram_tb"
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ccache_tmp = tmp_path / "ccache"
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ccache_tmp.mkdir()
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subprocess.run(
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[
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verilator,
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"--binary",
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"--timing",
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"-Wno-fatal",
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"--top-module",
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"psram_tb",
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"-I" + str(generated / "rtl"),
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"-I" + str(ROOT / "rtl/ip/memory"),
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"-I" + str(ROOT / "rtl/managed/clusterip/common/rtl"),
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"-I" + str(ROOT / "rtl/managed/clusterip/common/rtl/interface"),
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"-I" + str(ROOT / "rtl/managed/clusterip/common/rtl/utils"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/interface/axi4_if.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/interface/apb4_if.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/interface/axi4_addr_gen.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/utils/xchecker.sv"),
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str(ROOT / "rtl/ip/memory/psram_pkg.sv"),
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str(ROOT / "rtl/ip/memory/psram_axi4.sv"),
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str(ROOT / "rtl/ip/memory/psram_core.sv"),
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str(ROOT / "rtl/ip/memory/psram_phy.sv"),
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str(ROOT / "rtl/ip/memory/psram_reg.sv"),
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str(ROOT / "rtl/ip/memory/apb4_psram.sv"),
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str(ROOT / "rtl/mini/dv/model/ESP_PSRAM64H.sv"),
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str(ROOT / "tests/rtl/psram_tb.sv"),
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"-Mdir",
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str(tmp_path / "obj"),
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"-o",
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str(output),
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],
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check=True,
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text=True,
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capture_output=True,
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env={
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**os.environ,
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"CCACHE_DIR": str(ccache_tmp),
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"CCACHE_TEMPDIR": str(ccache_tmp),
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},
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)
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result = subprocess.run([output], check=True, text=True, capture_output=True)
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assert "PSRAM controller integration test passed" in result.stdout
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def test_psram_handwritten_register_offsets_match_hal() -> None:
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rtl_text = (ROOT / "rtl/ip/memory/psram_define.svh").read_text(encoding="utf-8")
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hal_text = (ROOT / "crt/src/hal/psram.c").read_text(encoding="utf-8")
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rtl_offsets = {
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name: int(value, 16)
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for name, value in re.findall(
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r"`define\s+APB4_PSRAM_([A-Z0-9_]+)\s+12'h([0-9A-Fa-f]+)",
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rtl_text,
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)
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}
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hal_offsets = {
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name: int(value, 16)
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for name, value in re.findall(
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r"#define\s+RS_PSRAM_([A-Z0-9_]+)_OFFSET\s+UINT32_C\(0x([0-9A-Fa-f]+)\)",
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hal_text,
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)
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}
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assert hal_offsets
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for name, value in hal_offsets.items():
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rtl_name = "CHIP0_ID_LO" if name == "CHIP_ID_BASE" else name
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assert rtl_offsets[rtl_name] == value
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