mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 22:55:14 +00:00
maksyuki
1eb342245c
- Replace onewire interface with ws2812 interface in retrosoc module. - Include ws2812_math.c in C test sources. - Add ws2812 header in test_runtime.c and implement ws2812 helper tests. - Update ribp_topology_tb and soc_irq_topology_tb to handle ws2812 interface. - Create ws2812_dma_tb and ws2812_tb for testing WS2812 DMA and waveform functionality. - Enhance test_script_tools.py to include ws2812 in formal filelists. - Modify test_soc_topology.py to ensure proper IRQ mapping for ws2812. - Introduce test_ws2812.py for WS2812 register, waveform, and streaming regression tests.
299 lines
9.5 KiB
Systemverilog
299 lines
9.5 KiB
Systemverilog
`timescale 1ns / 1ps
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`include "ws2812_define.svh"
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module ws2812_tb;
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localparam int FIFO_DEPTH = 4;
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localparam int BIT_CYCLES = 4;
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localparam int T0H_CYCLES = 1;
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localparam int T1H_CYCLES = 3;
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localparam int RESET_CYCLES = 5;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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ribp_if ribp ();
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ws2812_if ws2812 ();
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logic monitor_enable = 1'b0;
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logic [23:0] expected_pixels [0:7];
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integer expected_pixel_count = 0;
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integer observed_pixel = 0;
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integer observed_bit = 0;
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integer observed_cycle = 0;
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integer expected_bit_cycles = BIT_CYCLES;
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integer expected_t0h_cycles = T0H_CYCLES;
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integer expected_t1h_cycles = T1H_CYCLES;
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integer reset_low_cycles = 0;
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integer test_stage = 0;
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always #5 clk_i = ~clk_i;
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initial begin
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repeat (10000) @(posedge clk_i);
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$fatal(1, "WS2812 test timeout at stage %0d state=%0d valid=%b ready=%b", test_stage,
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u_dut.u_ws2812_core.s_state_q, ribp.valid, ribp.ready);
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end
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ribp_ws2812 #(
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.TX_FIFO_DEPTH(FIFO_DEPTH)
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) u_dut (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.ribp (ribp),
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.ws2812 (ws2812)
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);
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task automatic ribp_write(input logic [31:0] address, input logic [31:0] data,
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input logic [3:0] strobe, input logic expected_error,
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output integer wait_cycles);
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begin
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@(negedge clk_i);
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ribp.addr = address;
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ribp.wdata = data;
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ribp.wstrb = strobe;
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ribp.valid = 1'b1;
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wait_cycles = 0;
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while (!ribp.ready) begin
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@(posedge clk_i);
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#1;
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wait_cycles = wait_cycles + 1;
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end
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if (ribp.resp_err !== expected_error) begin
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$fatal(1, "write %h error=%b expected=%b", address, ribp.resp_err, expected_error);
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end
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@(negedge clk_i);
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ribp.valid = 1'b0;
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ribp.wstrb = '0;
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end
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endtask
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task automatic ribp_read(input logic [31:0] address, input logic expected_error,
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output logic [31:0] data);
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begin
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@(negedge clk_i);
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ribp.addr = address;
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ribp.wdata = '0;
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ribp.wstrb = '0;
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ribp.valid = 1'b1;
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while (!ribp.ready) begin
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@(posedge clk_i);
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#1;
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end
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if (ribp.resp_err !== expected_error) begin
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$fatal(1, "read %h error=%b expected=%b", address, ribp.resp_err, expected_error);
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end
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data = ribp.rdata;
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@(negedge clk_i);
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ribp.valid = 1'b0;
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end
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endtask
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task automatic write_ok(input logic [31:0] address, input logic [31:0] data);
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integer ignored_wait;
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begin
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ribp_write(address, data, 4'hF, 1'b0, ignored_wait);
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end
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endtask
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task automatic wait_until_idle;
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logic [31:0] status;
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begin
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status = 32'h1;
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while (status[`WS2812_STATUS_BUSY]) begin
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ribp_read(`RIBP_WS2812_STATUS, 1'b0, status);
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end
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end
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endtask
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task automatic configure_timing;
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begin
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write_ok(`RIBP_WS2812_BIT_CYCLES, BIT_CYCLES);
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write_ok(`RIBP_WS2812_T0H_CYCLES, T0H_CYCLES);
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write_ok(`RIBP_WS2812_T1H_CYCLES, T1H_CYCLES);
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write_ok(`RIBP_WS2812_RESET_CYCLES, RESET_CYCLES);
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write_ok(`RIBP_WS2812_FIFO_WATERMARK, 3);
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write_ok(`RIBP_WS2812_INTR_ENABLE, 4'hF);
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end
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endtask
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always @(posedge clk_i) begin
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#1;
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if (!rst_n_i && ws2812.dat_o !== 1'b0) begin
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$fatal(1, "WS2812 output is not low during reset");
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end
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if (monitor_enable && u_dut.s_busy && !u_dut.s_reset_active) begin
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integer high_cycles;
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logic expected_data;
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high_cycles = expected_pixels[observed_pixel][23-observed_bit] ? expected_t1h_cycles :
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expected_t0h_cycles;
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expected_data = observed_cycle < high_cycles;
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if (ws2812.dat_o !== expected_data) begin
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$fatal(1, "waveform mismatch pixel=%0d bit=%0d cycle=%0d", observed_pixel, observed_bit,
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observed_cycle);
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end
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observed_cycle = observed_cycle + 1;
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if (observed_cycle == expected_bit_cycles) begin
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observed_cycle = 0;
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observed_bit = observed_bit + 1;
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if (observed_bit == 24) begin
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observed_bit = 0;
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observed_pixel = observed_pixel + 1;
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end
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end
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end
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if (monitor_enable && u_dut.s_reset_active) begin
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if (ws2812.dat_o !== 1'b0) begin
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$fatal(1, "WS2812 output is high during latch/reset");
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end
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reset_low_cycles = reset_low_cycles + 1;
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end
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end
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task automatic begin_monitor(input integer pixel_count);
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begin
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observed_pixel = 0;
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observed_bit = 0;
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observed_cycle = 0;
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reset_low_cycles = 0;
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expected_pixel_count = pixel_count;
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monitor_enable = 1'b1;
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end
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endtask
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task automatic end_monitor(input logic expect_complete_frame);
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begin
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monitor_enable = 1'b0;
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if (expect_complete_frame && observed_pixel != expected_pixel_count) begin
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$fatal(1, "observed %0d pixels, expected %0d", observed_pixel, expected_pixel_count);
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end
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if (reset_low_cycles < RESET_CYCLES) begin
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$fatal(1, "latch/reset low interval was only %0d cycles", reset_low_cycles);
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end
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end
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endtask
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initial begin
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logic [31:0] value;
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integer wait_cycles;
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ribp.valid = 1'b0;
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ribp.addr = '0;
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ribp.wdata = '0;
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ribp.wstrb = '0;
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repeat (3) @(posedge clk_i);
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rst_n_i = 1'b1;
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test_stage = 1;
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ribp_read(`RIBP_WS2812_IP_INFO, 1'b0, value);
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if (value !== 32'h1804_0100) begin
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$fatal(1, "unexpected IP_INFO %h", value);
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end
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ribp_read(`RIBP_WS2812_STATUS, 1'b0, value);
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if (value[`WS2812_STATUS_CONFIG_VALID] || !value[`WS2812_STATUS_FIFO_EMPTY]) begin
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$fatal(1, "unexpected reset status %h", value);
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end
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ribp_read(`RIBP_WS2812_CTRL, 1'b1, value);
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ribp_write(8'h02, 32'd1, 4'hF, 1'b1, wait_cycles);
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ribp_read(32'h00000100, 1'b1, value);
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ribp_write(`RIBP_WS2812_TXDATA, 24'h112233, 4'h7, 1'b1, wait_cycles);
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write_ok(`RIBP_WS2812_TXDATA, 24'h112233);
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write_ok(`RIBP_WS2812_FRAME_WORDS, 1);
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ribp_write(`RIBP_WS2812_CTRL, 32'h1, 4'hF, 1'b1, wait_cycles);
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ribp_read(`RIBP_WS2812_ERROR_STATUS, 1'b0, value);
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if (!value[`WS2812_ERROR_CONFIG]) begin
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$fatal(1, "invalid timing did not set CONFIG error");
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end
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write_ok(`RIBP_WS2812_ERROR_STATUS, 32'h7);
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write_ok(`RIBP_WS2812_CTRL, 32'h4);
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configure_timing();
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ribp_read(`RIBP_WS2812_STATUS, 1'b0, value);
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if (!value[`WS2812_STATUS_CONFIG_VALID]) begin
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$fatal(1, "legal timing was not accepted");
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end
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test_stage = 2;
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for (integer index = 0; index < FIFO_DEPTH; index = index + 1) begin
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write_ok(`RIBP_WS2812_TXDATA, index);
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end
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ribp_write(`RIBP_WS2812_TXDATA, 32'h55, 4'hF, 1'b1, wait_cycles);
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write_ok(`RIBP_WS2812_CTRL, 32'h4);
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write_ok(`RIBP_WS2812_ERROR_STATUS, 32'h7);
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write_ok(`RIBP_WS2812_INTR_STATE, 32'hF);
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test_stage = 3;
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expected_pixels[0] = 24'h800001;
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expected_pixels[1] = 24'h010203;
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expected_pixels[2] = 24'hA5A5A5;
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expected_pixels[3] = 24'h5A5A5A;
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expected_pixels[4] = 24'hFFFFFF;
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expected_pixels[5] = 24'h000000;
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for (integer index = 0; index < FIFO_DEPTH; index = index + 1) begin
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write_ok(`RIBP_WS2812_TXDATA, expected_pixels[index]);
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end
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write_ok(`RIBP_WS2812_FRAME_WORDS, 6);
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begin_monitor(6);
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write_ok(`RIBP_WS2812_CTRL, 32'h1);
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write_ok(`RIBP_WS2812_TXDATA, expected_pixels[4]);
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ribp_write(`RIBP_WS2812_TXDATA, expected_pixels[5], 4'hF, 1'b0, wait_cycles);
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if (wait_cycles < (BIT_CYCLES * 20)) begin
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$fatal(1, "full FIFO write was not backpressured: %0d cycles", wait_cycles);
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end
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wait_until_idle();
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end_monitor(1'b1);
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ribp_read(`RIBP_WS2812_INTR_STATE, 1'b0, value);
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if ((value & 32'h3) != 32'h3 || !ws2812.irq_o) begin
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$fatal(1, "done/low-watermark interrupt missing: %h", value);
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end
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write_ok(`RIBP_WS2812_INTR_STATE, 32'hF);
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if (ws2812.irq_o) begin
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$fatal(1, "IRQ did not clear");
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end
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test_stage = 4;
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expected_pixels[0] = 24'h123456;
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write_ok(`RIBP_WS2812_TXDATA, expected_pixels[0]);
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write_ok(`RIBP_WS2812_FRAME_WORDS, 2);
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begin_monitor(1);
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write_ok(`RIBP_WS2812_CTRL, 32'h1);
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wait_until_idle();
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end_monitor(1'b1);
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ribp_read(`RIBP_WS2812_ERROR_STATUS, 1'b0, value);
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if (!value[`WS2812_ERROR_UNDERFLOW]) begin
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$fatal(1, "underflow was not reported");
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end
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ribp_read(`RIBP_WS2812_FIFO_LEVEL, 1'b0, value);
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if (value != 0) begin
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$fatal(1, "underflow did not flush FIFO");
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end
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write_ok(`RIBP_WS2812_ERROR_STATUS, 32'h7);
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write_ok(`RIBP_WS2812_INTR_STATE, 32'hF);
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test_stage = 5;
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expected_pixels[0] = 24'hABCDEF;
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expected_pixels[1] = 24'h765432;
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write_ok(`RIBP_WS2812_TXDATA, expected_pixels[0]);
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write_ok(`RIBP_WS2812_TXDATA, expected_pixels[1]);
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write_ok(`RIBP_WS2812_FRAME_WORDS, 2);
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begin_monitor(2);
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write_ok(`RIBP_WS2812_CTRL, 32'h1);
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repeat (8) @(posedge clk_i);
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write_ok(`RIBP_WS2812_CTRL, 32'h2);
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wait_until_idle();
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end_monitor(1'b0);
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ribp_read(`RIBP_WS2812_INTR_STATE, 1'b0, value);
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if (!value[`WS2812_INTR_ABORTED]) begin
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$fatal(1, "abort completion was not reported");
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end
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write_ok(`RIBP_WS2812_INTR_TEST, 32'h1);
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if (!ws2812.irq_o) begin
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$fatal(1, "interrupt test did not assert IRQ");
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end
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write_ok(`RIBP_WS2812_INTR_STATE, 32'hF);
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$display("WS2812 register, waveform, streaming, and error test passed");
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$finish;
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end
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endmodule
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