maksyuki
8d735aafbd
- Adjusted slot assignments in to reflect new peripheral mappings. - Updated to validate new OpenC906 configurations, including generator and profile checks. - Modified to reference the new Std-series VexiiRiscv generator. - Changed cache maintenance instructions in to align with C906 specifications. - Revised assertions in to account for internal unit removals. - Updated to reflect changes in peripheral interface counts and policies. - Added new test file to ensure preservation of the frozen HP configuration in the Std-series generator.
5.3 KiB
Third-party attribution
The Mini high-performance (HP) core is the pre-generated T-Head OpenC906 RTL
from XUANTIE-RV/openc906, locked at
commit b0c06eb1f8b3bae663bd8b87eac89ff48e68a57f in
dependencies/dependencies.lock.json and installed below
.cache/retrosoc/sources/openc906. OpenC906 is licensed under Apache-2.0; its
copyright and license files remain in the locked checkout and are not copied
into this repository. The single retroSoC-controlled substitution is the
reviewed hart-ID override rtl/mini/ip_overrides/aq_sysio_kid.v, which
retains the upstream Apache-2.0 header.
The optional HP RT-Thread kernel is official RT-Thread v5.3.0, commit
99428a1e7f7447955aa860f7c969273a12095b8f, from
RT-Thread/rt-thread. It is licensed
under Apache-2.0. Its original copyright/license files remain in the locked
managed checkout; only the retroSoC BSP is repository-owned. Redistribution of
built RT-Thread images must retain the applicable upstream notices.
This repository contains RTL source files that retain copyright and attribution information from third-party open-source projects in their original file headers. The following projects are explicitly referenced in the RTL sources currently present in this repository.
1. ETH Zurich and University of Bologna
Several RTL files retain the original copyright notice from ETH Zurich and University of Bologna, including files under the following paths:
- rtl/managed/clusterip/**
- rtl/managed/mpw/core/username7/ibex/**
- rtl/tech/tc_clk.sv
- rtl/ip/memory/opipsram_phy.sv
- rtl/ip/memory/opipsram_trx.sv
- rtl/tech/tc_opipsram_delay.sv
The tc_clk.sv header and the adapted OPI PSRAM PHY files state the
Solderpad Hardware License, Version 0.51 (SHL-0.51). The OPI PSRAM PHY
files are adapted from PULP Platform HyperBus v0.0.4 at commit
80de8df600edc5d7956a94c9d42f911d6e61efd7; each preserves the source-file
authors and records retroSoC's modifications. The exact license text is in
licenses/PULP_Platform-SHL-0.51.
2. Ravenna / PicoRV32 in ASIC
The following RTL files retain the original header from the Ravenna example SoC project, which refers to a design using PicoRV32 in ASIC:
- rtl/ip/peripheral/gpio.sv
- rtl/ip/peripheral/timer.sv
- rtl/ip/serial/uart.sv
The preserved notice attributes the work to Clifford Wolf and Tim Edwards.
3. Hirosh Dabui
The SDRAM controller implementation in rtl/ip/memory/sdram_core.sv retains the original copyright notice attributed to Hirosh Dabui.
4. EmbedFire
Several SPI SD card related RTL files retain the original attribution to EmbedFire and refer to source files such as sd_init.v, sd_write.v, sd_read.v, and data_rw_ctrl.v:
- rtl/ip/storage/spisd_core.sv
- rtl/ip/storage/spisd_data.sv
- rtl/ip/storage/spisd_init.sv
- rtl/ip/storage/spisd_read.sv
- rtl/ip/storage/spisd_write.sv
These headers state that the original code was published on GitHub by EmbedFire, but that the original license was not specified in the retained header.
5. Device simulation models
The simulation-only models under rtl/model/ retain their upstream notices
and source formatting. The AT24 model is imported from the retroSoC I2C
repository, the microphone model from the retroSoC I2S repository, and the
W25Q128JVxIM model from the retroSoC SPI repository. The Winbond model retains
its original Winbond Electronics Corporation copyright and "All Rights
Reserved" notice; its inclusion does not relicense it under Mulan PSL v2.
6. Notes on redistribution
The optional checksum-locked SKY130 SRAM artifact is generated with OpenRAM at
the revision recorded in its manifest. OpenRAM is distributed under the BSD
3-Clause License; the SkyWater-provided SRAM build-space used by the generator
is distributed under Apache License 2.0. The artifact retains both exact
license texts and is materialized only below the ignored .cache/ tree.
The preserved third-party notices are included to maintain attribution for code that was adapted or reused in this repository. They do not replace the repository's main license declaration. The retroSoC project itself is distributed under the Mulan PSL v2 license.
7. Typst publication diagram packages
The manual publication builder uses these checksum-locked third-party packages. Their original sources and notices remain in the verified package caches.
| Package | Authors | License | Original text |
|---|---|---|---|
| bytefield 0.0.8 | Jomaway https://github.com/jomaway | MIT | Exact license |
| rivet 0.3.1 | Louis Heredero https://git.kb28.ch/HEL | Apache-2.0 | Exact license |
| blockcell 0.1.0 | @daleione | MIT | Exact license |
| circuiteria 0.2.1 | Louis Heredero https://git.kb28.ch/HEL | Apache-2.0 | Exact license |
| cetz 0.3.4 | Johannes Wolf https://github.com/johannes-wolf; fenjalien https://github.com/fenjalien | LGPL-3.0-or-later | Exact license |
| tidy 0.3.0 | Mc-Zen https://github.com/Mc-Zen | MIT | Exact license |
| oxifmt 0.2.1 | PgBiel https://github.com/PgBiel | MIT-0 | Exact license |