mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
952b060a70
Integrate RNG, CRC, WS2812, Crypto, I2S master and the SDIO private AXI owner on SAFE24. Preserve the 128 KiB main SRAM and six private Crypto macros, add product-specific DMA assignments and reject unsupported SDK operations.
Correct APB read strobes, I2S receive assembly and SDIO command timing, backpressure and descriptor retirement. Add pin-level workloads, source-bound evidence checks and publication/commercial consumer compatibility.
Validation of the final P6 worktree: 1726 pytest tests passed with one optional pypdf skip (exit 0, 4021.61 seconds; terminal session 36439). Both PDKs passed both RTL simulators, netlist boot and 38-macro binding checks. Shared formal, Mini compatibility and software/source quality gates passed.
Evidence remains attributed to the retained dirty-worktree snapshots based on b3b30a72cd under build/ics55-tiny-2026-10-12-11-50-2eb98c0e1fae/meta/tiny-r2-p6/. Timing is negative and warning observations are not promoted. This commit does not accept P6, qualify physical operation or enable P7.
78 lines
3.5 KiB
Tcl
78 lines
3.5 KiB
Tcl
# P4 structural timing prerequisites, common to both supported Tiny PDKs.
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# Negative timing remains observational; missing/incorrect clock objects do not.
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set p4_dir [file dirname $::env(OPENSTA_REPORT)]
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set p4_ram [get_cells -hierarchical -filter {ref_name == RM_IHPSG13_1P_1024x32_c2_bm_bist}]
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set p4_clock_pin A_CLK
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if {[llength $p4_ram] == 0} {
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set p4_ram [get_cells -hierarchical -filter {ref_name == ics55_ecos_sram_1024x32_m8}]
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set p4_clock_pin CLK
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}
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if {[llength $p4_ram] != 38} { error "P6 requires 32 main SRAM and six private Crypto macros" }
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set p6_all_ram $p4_ram
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set p4_ram {}
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set p6_crypto {}
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set p6_crypto_expected {}
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for {set bank 0} {$bank < 6} {incr bank} {
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lappend p6_crypto_expected [format {u_soc.u_crypto.u_storage.gen_bank[%d].gen_macro.u_sram.u_mem} $bank]
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}
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set p6_crypto_seen {}
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foreach cell $p6_all_ram {
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set name [string map {/ .} [get_full_name $cell]]
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set is_crypto 0
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foreach expected $p6_crypto_expected {
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if {[string equal [string range $name end-[expr {[string length $expected]-1}] end] $expected]} {
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lappend p6_crypto_seen $expected
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set is_crypto 1
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}
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}
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if {$is_crypto} { lappend p6_crypto $cell } else { lappend p4_ram $cell }
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}
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if {[llength $p4_ram] != 32 || [lsort $p6_crypto_seen] ne [lsort $p6_crypto_expected]} {
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error "P6 private/main SRAM hierarchy mismatch"
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}
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set p4_expected {}
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for {set group 0} {$group < 4} {incr group} {
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for {set bank 0} {$bank < 8} {incr bank} {
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lappend p4_expected [format {u_soc.u_sram.gen_group[%d].u_group.gen_bank[%d].u_ram.u_mem} $group $bank]
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}
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}
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set p4_seen {}
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foreach cell $p4_ram {
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set name [string map {/ .} [get_full_name $cell]]
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foreach expected $p4_expected {
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if {[string equal [string range $name end-[expr {[string length $expected]-1}] end] $expected]} {
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lappend p4_seen $expected
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}
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}
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}
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if {[lsort $p4_seen] ne [lsort $p4_expected]} { error "P4 macro group hierarchy mismatch" }
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set p4_source [get_pins -quiet {u_clock_buffer/clk_o}]
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if {[llength $p4_source] != 1} { error "P4 SYS source missing" }
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set p4_direct {}
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foreach pin [get_fanout -from $p4_source -flat -pin_levels 1 -trace_arcs all] {
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dict set p4_direct [get_full_name $pin] 1
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}
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set p4_clock_report [open $p4_dir/p4-clock-bindings.rpt w]
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foreach cell [concat $p4_ram $p6_crypto] {
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set clocks {}
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foreach pin [get_pins -of_objects $cell] {
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if {[string match "*/$p4_clock_pin" [get_full_name $pin]]} { lappend clocks $pin }
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}
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if {[llength $clocks] != 1} { error "P4 macro clock pin missing" }
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set name [get_full_name [lindex $clocks 0]]
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if {![dict exists $p4_direct $name]} { error "P4 SRAM clock is not direct SYS: $name" }
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puts $p4_clock_report $name
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}
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set p4_cpu [get_pins -hierarchical -quiet {*u_hazard3_cpu_2port*/CLK *u_hazard3_cpu_2port*/CK *u_hazard3_cpu_2port*/CKN}]
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set p4_front [get_pins -hierarchical -quiet {*u_cpu_mem*/CLK *u_cpu_mem*/CK *u_cpu_mem*/CKN}]
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if {[llength $p4_cpu] == 0 || [llength $p4_front] == 0} { error "P4 CPU/frontend clock endpoints missing" }
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foreach pin [concat $p4_cpu $p4_front] {
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set name [get_full_name $pin]
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if {![dict exists $p4_direct $name]} { error "P4 CPU/frontend does not share SYS: $name" }
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}
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puts $p4_clock_report "CPU clock endpoints: [llength $p4_cpu]"
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puts $p4_clock_report "Frontend clock endpoints: [llength $p4_front]"
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close $p4_clock_report
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puts "TINY_R2_P4_BINDING_PASS: four groups, 32 macros, common CPU/SRAM SYS; not timing qualification"
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puts "TINY_R2_P6_BINDING_PASS: six private Crypto macros on SAFE24 PCLK; no capacity alias"
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