mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
bc48cec74a
Integrate the Tiny RCU, normalized REF24 control, external-input profiles, single PLL backend, SYS/MEM/PCLK clocks, CPU-only WFI gating, peripheral lifecycle control and retained debug behavior. Keep CPU and all 32 main SRAM macros on SYS and the six private Crypto macros on PCLK. Add the handwritten RCU register/HAL contract, RS_EBUSY, bounded SDK operations and focused firmware. Preserve shared-IP defaults and the ICS55/PLL SAFE24 boot and explicit IHP130/no-PLL compatibility profiles. Use APB/AXI domain bridges and source-owned response holders to preserve backpressured responses, complete aborted bursts and prevent stale replay. Verify production DMA source-reset drain and common XPI endpoint reset with extracted integration bindings and an independent scoreboard. Add source-bound macro/clock audits, SAFE24 observational STA constraints and commercial-adapter host checks. No P8 functionality or operating-point qualification is included. See TINY-R2-P7 in docs/ip/tiny-soc.md. Validation: 54 P7 directed tests pass, including both simulators, ten source-reset ratio runs and two expected-negative drain mutations. RTL format/style, clock/reset inventory, Ruff and both Tiny PDK PR dry-runs pass. Retained 06-00 synthesis and strict netlist boots pass for both PDKs; STA remains negative and observational. Source comparison confirms only the follow-up tests changed after that backend campaign. Evidence: build/ics55-tiny-2026-10-14-06-00-ff4b5cef6eb5/meta/ tiny-r2-p7-source-reset/summary.json. Earlier firmware, HAL and compatibility results and the non-clean full-suite attempt retain their original attribution. Full Icarus firmware is deferred to final Tiny qualification; this commit does not constitute human phase acceptance or physical signoff.
23 lines
1.5 KiB
Tcl
23 lines
1.5 KiB
Tcl
# P7 uses a dedicated, provenance-checked Python macro/clock audit. Historical
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# P1/P4 checks retain their direct-SYS/parked-PLL assumptions unchanged.
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set p7_dir [file dirname $::env(OPENSTA_REPORT)]
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foreach clock {clk_aon clk_system clk_memory clk_peripheral clk_audio clk_jtag clk_sys_div2 clk_sys_div4 clk_clkout_source} {
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if {[llength [get_clocks -quiet $clock]] != 1} { error "P7 clock missing: $clock" }
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}
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set p7_pll [get_cells -hierarchical -quiet -filter {ref_name == PLL_TOP}]
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if {[llength $p7_pll] > 1} { error "P7 contains multiple PLL macros" }
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if {[llength $p7_pll] == 1} {
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# The analysis is explicitly the cold SAFE24 boot operating state.
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set p7_enable [get_pins -quiet "[get_full_name [lindex $p7_pll 0]]/EN"]
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if {[llength $p7_enable] != 1} { error "P7 PLL enable pin missing" }
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set_case_analysis 0 $p7_enable
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}
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report_clock_properties > $p7_dir/clocks.rpt
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check_setup -verbose > $p7_dir/coverage.rpt
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report_check_types -recovery -removal -min_pulse_width -min_period -max_slew -max_capacitance -max_fanout -violators -verbose > $p7_dir/constraint-violations.rpt
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foreach domain {system memory peripheral aon} {
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report_checks -path_group clk_$domain -path_delay max -group_path_count 20 -fields {capacitance slew fanout} > $p7_dir/$domain-setup.rpt
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report_checks -path_group clk_$domain -path_delay min -group_path_count 20 -fields {capacitance slew fanout} > $p7_dir/$domain-hold.rpt
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}
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puts "TINY_R2_P7_STA_OBSERVATION: SAFE24 boot only; not active PLL, routed or PVT qualification"
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