mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
bc48cec74a
Integrate the Tiny RCU, normalized REF24 control, external-input profiles, single PLL backend, SYS/MEM/PCLK clocks, CPU-only WFI gating, peripheral lifecycle control and retained debug behavior. Keep CPU and all 32 main SRAM macros on SYS and the six private Crypto macros on PCLK. Add the handwritten RCU register/HAL contract, RS_EBUSY, bounded SDK operations and focused firmware. Preserve shared-IP defaults and the ICS55/PLL SAFE24 boot and explicit IHP130/no-PLL compatibility profiles. Use APB/AXI domain bridges and source-owned response holders to preserve backpressured responses, complete aborted bursts and prevent stale replay. Verify production DMA source-reset drain and common XPI endpoint reset with extracted integration bindings and an independent scoreboard. Add source-bound macro/clock audits, SAFE24 observational STA constraints and commercial-adapter host checks. No P8 functionality or operating-point qualification is included. See TINY-R2-P7 in docs/ip/tiny-soc.md. Validation: 54 P7 directed tests pass, including both simulators, ten source-reset ratio runs and two expected-negative drain mutations. RTL format/style, clock/reset inventory, Ruff and both Tiny PDK PR dry-runs pass. Retained 06-00 synthesis and strict netlist boots pass for both PDKs; STA remains negative and observational. Source comparison confirms only the follow-up tests changed after that backend campaign. Evidence: build/ics55-tiny-2026-10-14-06-00-ff4b5cef6eb5/meta/ tiny-r2-p7-source-reset/summary.json. Earlier firmware, HAL and compatibility results and the non-clean full-suite attempt retain their original attribution. Full Icarus firmware is deferred to final Tiny qualification; this commit does not constitute human phase acceptance or physical signoff.
227 lines
9.5 KiB
Systemverilog
227 lines
9.5 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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`timescale 1ns / 1ps
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module apb4_sdio #(
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parameter int InputClockHz = 72_000_000,
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parameter bit UseRuntimeClockHz = 1'b0,
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parameter int AddrWidth = 32,
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parameter int DataWidth = 32,
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parameter int DescCount = 16
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) (
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// verilog_format: off -- preserve the APB, AXI, and pad column alignment
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output logic lifecycle_idle_o,
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input logic clk_i,
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input logic rst_n_i,
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apb4_if.slave apb4,
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axi4_if.master dma_axi4,
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sdio_if.dut sdio,
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input logic [31:0] clock_hz_i
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// verilog_format: on
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);
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logic s_busy;
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logic s_host_enable;
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logic s_host_irq_enable;
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logic s_clock_enable;
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logic [ 15:0] s_half_period;
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logic [ 1:0] s_bus_width;
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logic [ 31:0] s_timeout_cmd;
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logic [ 31:0] s_timeout_data;
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logic [ 31:0] s_timeout_busy;
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logic [ 5:0] s_cmd_index;
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logic [ 31:0] s_cmd_arg;
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sdio_pkg::sdio_resp_type_e s_cmd_resp_type;
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logic s_cmd_crc_check;
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logic s_cmd_index_check;
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logic s_cmd_start;
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logic [ 15:0] s_block_size;
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logic [ 15:0] s_block_count;
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logic s_data_direction;
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logic s_data_dma_enable;
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logic s_data_block_mode;
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logic s_data_fixed_addr;
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logic s_data_start;
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logic s_pio_wvalid;
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logic [ 31:0] s_pio_wdata;
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logic [ 3:0] s_pio_wstrb;
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logic [ 31:0] s_desc_base;
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logic [ 15:0] s_desc_count;
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logic s_dma_start;
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logic s_dma_abort;
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logic s_host_abort;
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logic s_irq_dat1_enable;
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logic s_irq;
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logic [ 31:0] s_status;
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logic [ 31:0] s_clock_actual;
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logic [ 31:0] s_cmd_status;
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logic [135:0] s_response;
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logic [ 31:0] s_data_status;
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logic [ 31:0] s_fifo_status;
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logic [ 31:0] s_dma_status;
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logic [ 31:0] s_current_desc;
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logic [ 31:0] s_bytes_done;
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logic [ 31:0] s_dma_err_addr;
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logic [ 31:0] s_dma_err;
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logic [ 31:0] s_err_stat;
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logic [ 5:0] s_last_cmd;
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logic [ 31:0] s_crc_err_count;
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logic [ 31:0] s_timeout_count;
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logic [ 31:0] s_axi_err_count;
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logic [ 31:0] s_stall_count;
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logic [ 7:0] s_irq_event;
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logic [ 31:0] s_pio_rdata;
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logic s_pio_valid;
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logic s_pio_ready;
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logic s_pio_read_consume;
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sdio_if u_sdio_core_if ();
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logic s_bus_busy;
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assign s_bus_busy = dma_axi4.awvalid || dma_axi4.arvalid || dma_axi4.wvalid;
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assign lifecycle_idle_o = !s_busy && !s_clock_enable && !s_bus_busy;
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assign u_sdio_core_if.cmd_di_i = sdio.cmd_di_i;
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assign u_sdio_core_if.dat_di_i = sdio.dat_di_i;
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assign sdio.sck_o = u_sdio_core_if.sck_o;
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assign sdio.cmd_oe_o = u_sdio_core_if.cmd_oe_o;
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assign sdio.cmd_do_o = u_sdio_core_if.cmd_do_o;
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assign sdio.dat_oe_o = u_sdio_core_if.dat_oe_o;
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assign sdio.dat_do_o = u_sdio_core_if.dat_do_o;
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sdio_reg u_sdio_reg (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.busy_i (s_busy),
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.status_i (s_status),
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.clock_actual_i (s_clock_actual),
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.cmd_status_i (s_cmd_status),
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.response_i (s_response),
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.data_status_i (s_data_status),
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.fifo_status_i (s_fifo_status),
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.dma_status_i (s_dma_status),
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.current_desc_i (s_current_desc),
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.bytes_done_i (s_bytes_done),
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.dma_error_addr_i (s_dma_err_addr),
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.dma_error_i (s_dma_err),
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.error_status_i (s_err_stat),
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.last_cmd_i (s_last_cmd),
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.crc_error_count_i (s_crc_err_count),
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.timeout_count_i (s_timeout_count),
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.axi_error_count_i (s_axi_err_count),
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.stall_count_i (s_stall_count),
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.irq_event_i (s_irq_event),
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.pio_rdata_i (s_pio_rdata),
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.pio_valid_i (s_pio_valid),
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.pio_ready_i (s_pio_ready),
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.pio_read_consume_o(s_pio_read_consume),
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.host_enable_o (s_host_enable),
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.host_irq_enable_o (s_host_irq_enable),
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.clock_enable_o (s_clock_enable),
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.half_period_o (s_half_period),
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.bus_width_o (s_bus_width),
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.timeout_cmd_o (s_timeout_cmd),
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.timeout_data_o (s_timeout_data),
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.timeout_busy_o (s_timeout_busy),
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.cmd_index_o (s_cmd_index),
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.cmd_arg_o (s_cmd_arg),
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.cmd_resp_type_o (s_cmd_resp_type),
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.cmd_crc_check_o (s_cmd_crc_check),
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.cmd_index_check_o (s_cmd_index_check),
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.cmd_start_o (s_cmd_start),
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.block_size_o (s_block_size),
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.block_count_o (s_block_count),
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.data_direction_o (s_data_direction),
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.data_dma_enable_o (s_data_dma_enable),
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.data_block_mode_o (s_data_block_mode),
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.data_fixed_addr_o (s_data_fixed_addr),
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.data_start_o (s_data_start),
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.pio_wvalid_o (s_pio_wvalid),
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.pio_wdata_o (s_pio_wdata),
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.pio_wstrb_o (s_pio_wstrb),
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.desc_base_o (s_desc_base),
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.desc_count_o (s_desc_count),
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.dma_start_o (s_dma_start),
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.dma_abort_o (s_dma_abort),
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.host_abort_o (s_host_abort),
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.irq_dat1_enable_o (s_irq_dat1_enable),
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.irq_o (s_irq),
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.apb4 (apb4)
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);
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sdio_core #(
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.InputClockHz (InputClockHz),
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.UseRuntimeClockHz(UseRuntimeClockHz),
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.AddrWidth (AddrWidth),
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.DataWidth (DataWidth),
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.DescCount (DescCount)
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) u_sdio_core (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.host_enable_i (s_host_enable),
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.clock_hz_i (clock_hz_i),
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.host_irq_enable_i (s_host_irq_enable),
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.clock_enable_i (s_clock_enable),
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.half_period_i (s_half_period),
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.bus_width_i (s_bus_width),
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.timeout_cmd_i (s_timeout_cmd),
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.timeout_data_i (s_timeout_data),
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.timeout_busy_i (s_timeout_busy),
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.cmd_index_i (s_cmd_index),
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.cmd_arg_i (s_cmd_arg),
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.cmd_resp_type_i (s_cmd_resp_type),
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.cmd_crc_check_i (s_cmd_crc_check),
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.cmd_index_check_i (s_cmd_index_check),
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.cmd_start_i (s_cmd_start),
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.block_size_i (s_block_size),
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.block_count_i (s_block_count),
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.data_direction_i (s_data_direction),
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.data_dma_enable_i (s_data_dma_enable),
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.data_block_mode_i (s_data_block_mode),
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.data_fixed_addr_i (s_data_fixed_addr),
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.data_start_i (s_data_start),
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.pio_wvalid_i (s_pio_wvalid),
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.pio_wdata_i (s_pio_wdata),
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.pio_wstrb_i (s_pio_wstrb),
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.desc_base_i (s_desc_base),
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.desc_count_i (s_desc_count),
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.dma_start_i (s_dma_start),
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.dma_abort_i (s_dma_abort),
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.host_abort_i (s_host_abort),
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.irq_dat1_enable_i (s_irq_dat1_enable),
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.status_o (s_status),
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.clock_actual_o (s_clock_actual),
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.cmd_status_o (s_cmd_status),
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.response_o (s_response),
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.data_status_o (s_data_status),
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.fifo_status_o (s_fifo_status),
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.dma_status_o (s_dma_status),
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.current_desc_o (s_current_desc),
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.bytes_done_o (s_bytes_done),
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.dma_error_addr_o (s_dma_err_addr),
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.dma_error_o (s_dma_err),
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.error_status_o (s_err_stat),
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.last_cmd_o (s_last_cmd),
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.crc_error_count_o (s_crc_err_count),
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.timeout_count_o (s_timeout_count),
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.axi_error_count_o (s_axi_err_count),
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.stall_count_o (s_stall_count),
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.irq_event_o (s_irq_event),
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.pio_rdata_o (s_pio_rdata),
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.pio_valid_o (s_pio_valid),
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.pio_ready_o (s_pio_ready),
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.pio_read_consume_i(s_pio_read_consume),
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.busy_o (s_busy),
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.sdio (u_sdio_core_if),
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.dma_axi4 (dma_axi4)
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);
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assign sdio.irq_o = s_irq;
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endmodule
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