mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
952b060a70
Integrate RNG, CRC, WS2812, Crypto, I2S master and the SDIO private AXI owner on SAFE24. Preserve the 128 KiB main SRAM and six private Crypto macros, add product-specific DMA assignments and reject unsupported SDK operations.
Correct APB read strobes, I2S receive assembly and SDIO command timing, backpressure and descriptor retirement. Add pin-level workloads, source-bound evidence checks and publication/commercial consumer compatibility.
Validation of the final P6 worktree: 1726 pytest tests passed with one optional pypdf skip (exit 0, 4021.61 seconds; terminal session 36439). Both PDKs passed both RTL simulators, netlist boot and 38-macro binding checks. Shared formal, Mini compatibility and software/source quality gates passed.
Evidence remains attributed to the retained dirty-worktree snapshots based on b3b30a72cd under build/ics55-tiny-2026-10-12-11-50-2eb98c0e1fae/meta/tiny-r2-p6/. Timing is negative and warning observations are not promoted. This commit does not accept P6, qualify physical operation or enable P7.
655 lines
27 KiB
Systemverilog
655 lines
27 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO THE WARRANTIES OF
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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`timescale 1ns / 1ps
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`include "axi4_define.svh"
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module sdio_dma #(
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parameter int AddrWidth = 32,
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parameter int DataWidth = 32,
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parameter int DescCount = 16
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) (
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input logic clk_i,
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input logic rst_n_i,
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input logic start_i,
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input logic abort_i,
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input logic direction_i,
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input logic [AddrWidth-1:0] desc_base_i,
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input logic [ 15:0] desc_count_i,
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input logic [ 31:0] total_bytes_i,
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input logic data_in_valid_i,
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output logic data_in_ready_o,
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input logic [ 31:0] data_in_i,
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input logic [ 3:0] data_in_strb_i,
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input logic data_in_last_i,
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output logic data_out_valid_o,
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input logic data_out_ready_i,
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output logic [ 31:0] data_out_o,
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output logic [ 3:0] data_out_strb_o,
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output logic data_out_last_o,
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output logic busy_o,
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output logic done_o,
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output logic error_o,
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output logic [ 7:0] error_code_o,
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output logic [AddrWidth-1:0] current_desc_o,
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output logic [ 31:0] bytes_done_o,
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output logic [AddrWidth-1:0] error_addr_o,
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output logic descriptor_irq_o,
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output logic abort_done_o,
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axi4_if.master dma_axi4
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);
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localparam logic [15:0] DescCountLimit = 16'(DescCount);
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typedef enum logic [3:0] {
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Idle,
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FetchStart,
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FetchWait,
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Validate,
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PayloadReadStart,
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PayloadReadWait,
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PayloadWriteStart,
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PayloadWriteWait,
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WritebackStart,
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WritebackWait,
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Terminal
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} dma_state_e;
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dma_state_e s_state_d, s_state_q;
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logic [AddrWidth-1:0] s_desc_addr_d, s_desc_addr_q;
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logic [15:0] s_desc_limit_d, s_desc_limit_q;
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logic [15:0] s_desc_index_d, s_desc_index_q;
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logic s_direction_d, s_direction_q;
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logic [31:0] s_total_bytes_d, s_total_bytes_q;
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logic [31:0] s_total_seen_d, s_total_seen_q;
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logic [31:0] s_total_done_d, s_total_done_q;
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logic [31:0] s_desc_progress_d, s_desc_progress_q;
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logic [4:0] s_burst_beats_d, s_burst_beats_q;
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logic [4:0] s_burst_index_d, s_burst_index_q;
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logic [31:0] s_desc_buffer_d, s_desc_buffer_q;
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logic [31:0] s_desc_count_d, s_desc_count_q;
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logic [31:0] s_desc_next_d, s_desc_next_q;
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logic [31:0] s_desc_control_d, s_desc_control_q;
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logic [31:0] s_writeback_control_d, s_writeback_control_q;
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logic [31:0] s_fetch_word_d[0:3];
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logic [31:0] s_fetch_word_q[0:3];
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logic s_desc_end_d, s_desc_end_q;
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logic s_desc_irq_d, s_desc_irq_q;
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logic s_fault_d, s_fault_q;
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logic [7:0] s_err_code_d, s_err_code_q;
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logic [AddrWidth-1:0] s_err_addr_d, s_err_addr_q;
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logic s_done_d, s_done_q;
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logic s_err_sticky_d, s_err_sticky_q;
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logic s_abort_pending_d, s_abort_pending_q;
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logic s_write_final_sent_d, s_write_final_sent_q;
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logic [4:0] s_write_beat_count_d, s_write_beat_count_q;
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logic s_descriptor_irq_d, s_descriptor_irq_q;
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logic s_abort_done_d, s_abort_done_q;
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logic s_read_start_valid;
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logic s_read_start_ready;
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logic [AddrWidth-1:0] s_read_addr;
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logic [ 4:0] s_read_beats;
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logic s_read_beat_valid;
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logic s_read_beat_ready;
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logic [DataWidth-1:0] s_read_data;
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logic [ 1:0] s_read_resp;
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logic s_read_last;
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logic s_read_expected_last;
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logic s_read_id_error;
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logic s_read_done;
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logic s_write_start_valid;
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logic s_write_start_ready;
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logic [AddrWidth-1:0] s_write_addr;
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logic [ 4:0] s_write_beats;
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logic s_write_data_valid;
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logic s_write_data_ready;
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logic [DataWidth-1:0] s_write_data;
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logic [ 3:0] s_write_strb;
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logic s_write_done;
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logic [ 1:0] s_write_resp;
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logic s_write_id_error;
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logic s_read_busy;
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logic s_write_busy;
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logic [ 31:0] s_payload_addr;
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logic [ 31:0] s_payload_left;
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logic [ 4:0] s_payload_beats;
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logic [ 31:0] s_burst_offset;
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logic [ 31:0] s_beat_left;
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logic [ 2:0] s_beat_bytes;
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logic [ 31:0] s_progress_after_beat;
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logic [ 2:0] s_input_bytes;
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logic s_axi_read_fault;
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logic s_axi_write_fault;
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function automatic logic [4:0] choose_burst(input logic [11:0] addr_low_i,
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input logic [31:0] bytes_i);
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logic [31:0] needed;
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logic [31:0] boundary;
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logic [31:0] selected;
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begin
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needed = (bytes_i + 32'd3) >> 2;
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boundary = (32'd4096 - {20'd0, addr_low_i}) >> 2;
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selected = needed;
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if (selected > 32'd16) selected = 32'd16;
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if (selected > boundary) selected = boundary;
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if (selected == 32'd0) selected = 32'd1;
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return selected[4:0];
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end
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endfunction
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function automatic logic [2:0] beat_bytes(input logic [31:0] bytes_i);
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return (bytes_i >= 32'd4) ? 3'd4 : bytes_i[2:0];
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endfunction
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function automatic logic strobe_valid(input logic [3:0] strb_i);
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return (strb_i != 4'd0) && ((strb_i & (strb_i + 4'd1)) == 4'd0);
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endfunction
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assign s_payload_addr = s_desc_buffer_q + s_desc_progress_q;
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assign s_payload_left = s_desc_count_q - s_desc_progress_q;
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assign s_payload_beats = choose_burst(s_payload_addr[11:0], s_payload_left);
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assign s_burst_offset = {27'd0, s_burst_index_q} << 2;
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assign s_beat_left = s_payload_left;
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assign s_beat_bytes = beat_bytes(s_beat_left);
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assign s_progress_after_beat = s_desc_progress_q + {29'd0, s_beat_bytes};
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assign s_input_bytes = count_strobe(data_in_strb_i);
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assign s_axi_read_fault = (s_read_resp != `AXI4_RESP_OKAY) || s_read_id_error ||
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(s_read_last != s_read_expected_last);
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assign s_axi_write_fault = (s_write_resp != `AXI4_RESP_OKAY) || s_write_id_error;
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function automatic logic [2:0] count_strobe(input logic [3:0] strb_i);
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logic [2:0] count;
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begin
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count = 3'd0;
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for (int index = 0; index < 4; index++) begin
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if (strb_i[index]) count = count + 1'b1;
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end
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return count;
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end
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endfunction
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assign s_read_start_valid = !abort_i &&
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((s_state_q == FetchStart) || (s_state_q == PayloadReadStart));
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assign s_read_addr = (s_state_q == FetchStart) ? s_desc_addr_q : s_payload_addr;
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assign s_read_beats = (s_state_q == FetchStart) ? 5'd4 : s_payload_beats;
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assign s_read_beat_ready = (s_state_q == FetchWait) ||
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((s_state_q == PayloadReadWait) &&
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(abort_i || s_abort_pending_q || data_out_ready_i));
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assign s_write_start_valid = (s_state_q == PayloadWriteStart) || (s_state_q == WritebackStart);
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assign s_write_addr = (s_state_q == PayloadWriteStart) ? s_payload_addr : s_desc_addr_q + 32'd12;
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assign s_write_beats = (s_state_q == PayloadWriteStart) ? s_payload_beats : 5'd1;
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assign s_write_data_valid = (s_state_q == PayloadWriteWait)
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? (s_abort_pending_q || data_in_valid_i)
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: (s_state_q == WritebackWait);
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assign s_write_data = (s_state_q == PayloadWriteWait && s_abort_pending_q)
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? '0
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: (s_state_q == WritebackWait ? s_writeback_control_q : data_in_i);
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assign s_write_strb = (s_state_q == PayloadWriteWait && s_abort_pending_q)
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? 4'b0000
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: (s_state_q == WritebackWait ? 4'b1111 : data_in_strb_i);
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assign data_in_ready_o = (s_state_q == PayloadWriteWait) && !s_abort_pending_q &&
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s_write_data_ready;
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assign data_out_valid_o = (s_state_q == PayloadReadWait) && s_read_beat_valid &&
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!s_abort_pending_q && !s_axi_read_fault;
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assign data_out_o = s_read_data;
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assign data_out_strb_o = (4'b0001 << s_beat_bytes) - 1'b1;
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assign data_out_last_o = s_desc_end_q && (s_progress_after_beat >= s_desc_count_q);
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assign busy_o = ((s_state_q != Idle) && (s_state_q != Terminal)) || s_read_busy || s_write_busy;
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assign done_o = s_done_q;
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assign error_o = s_err_sticky_q;
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assign error_code_o = s_err_code_q;
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assign current_desc_o = s_desc_addr_q;
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assign bytes_done_o = s_total_done_q;
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assign error_addr_o = s_err_addr_q;
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assign descriptor_irq_o = s_descriptor_irq_q;
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assign abort_done_o = s_abort_done_q;
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dma_axi4_master #(
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.AddrWidth (AddrWidth),
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.DataWidth (DataWidth),
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.MaxBurstBeats(16)
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) u_dma_axi4_master (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.clear_i (1'b0),
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.read_start_valid_i (s_read_start_valid),
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.read_start_ready_o (s_read_start_ready),
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.read_addr_i (s_read_addr),
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.read_beats_i (s_read_beats),
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.read_fixed_i (1'b0),
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.read_busy_o (s_read_busy),
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.read_beat_valid_o (s_read_beat_valid),
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.read_beat_ready_i (s_read_beat_ready),
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.read_data_o (s_read_data),
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.read_resp_o (s_read_resp),
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.read_last_o (s_read_last),
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.read_expected_last_o(s_read_expected_last),
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.read_id_error_o (s_read_id_error),
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.read_done_o (s_read_done),
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.write_start_valid_i (s_write_start_valid),
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.write_start_ready_o (s_write_start_ready),
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.write_addr_i (s_write_addr),
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.write_beats_i (s_write_beats),
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.write_fixed_i (1'b0),
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.write_busy_o (s_write_busy),
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.write_data_valid_i (s_write_data_valid),
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.write_data_ready_o (s_write_data_ready),
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.write_data_i (s_write_data),
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.write_strb_i (s_write_strb),
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.write_done_o (s_write_done),
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.write_resp_o (s_write_resp),
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.write_id_error_o (s_write_id_error),
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.axi4 (dma_axi4)
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);
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always_comb begin
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s_state_d = s_state_q;
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s_desc_addr_d = s_desc_addr_q;
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s_desc_limit_d = s_desc_limit_q;
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s_desc_index_d = s_desc_index_q;
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s_direction_d = s_direction_q;
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s_total_bytes_d = s_total_bytes_q;
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s_total_seen_d = s_total_seen_q;
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s_total_done_d = s_total_done_q;
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s_desc_progress_d = s_desc_progress_q;
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s_burst_beats_d = s_burst_beats_q;
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s_burst_index_d = s_burst_index_q;
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s_desc_buffer_d = s_desc_buffer_q;
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s_desc_count_d = s_desc_count_q;
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s_desc_next_d = s_desc_next_q;
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s_desc_control_d = s_desc_control_q;
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s_writeback_control_d = s_writeback_control_q;
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s_desc_end_d = s_desc_end_q;
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s_desc_irq_d = s_desc_irq_q;
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s_fault_d = s_fault_q;
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s_err_code_d = s_err_code_q;
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s_err_addr_d = s_err_addr_q;
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s_done_d = 1'b0;
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s_err_sticky_d = s_err_sticky_q;
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s_abort_pending_d = s_abort_pending_q;
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s_write_final_sent_d = s_write_final_sent_q;
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s_write_beat_count_d = s_write_beat_count_q;
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s_descriptor_irq_d = 1'b0;
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s_abort_done_d = 1'b0;
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for (int index = 0; index < 4; index++) begin
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s_fetch_word_d[index] = s_fetch_word_q[index];
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end
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if (s_state_q == Idle) begin
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if (start_i) begin
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s_desc_addr_d = desc_base_i;
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s_desc_limit_d = desc_count_i;
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s_desc_index_d = '0;
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s_direction_d = direction_i;
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s_total_bytes_d = total_bytes_i;
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s_total_seen_d = '0;
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s_total_done_d = '0;
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s_desc_progress_d = '0;
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s_fault_d = 1'b0;
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s_err_code_d = '0;
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s_err_addr_d = '0;
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s_err_sticky_d = 1'b0;
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s_abort_pending_d = 1'b0;
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if ((desc_base_i[3:0] != 4'b0000) || (desc_base_i[11:0] >= 12'hFF0) ||
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(desc_count_i == 16'd0) || (desc_count_i > DescCountLimit)) begin
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s_state_d = Terminal;
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s_done_d = 1'b1;
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s_fault_d = 1'b1;
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s_err_sticky_d = 1'b1;
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s_err_code_d = 8'h02;
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s_err_addr_d = desc_base_i;
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end else begin
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s_state_d = FetchStart;
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end
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end
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end else if (s_state_q == FetchStart) begin
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if (abort_i) begin
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s_fault_d = 1'b1;
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s_err_sticky_d = 1'b1;
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s_err_code_d = 8'h08;
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s_err_addr_d = s_desc_addr_q;
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s_state_d = Terminal;
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s_done_d = 1'b1;
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s_abort_done_d = 1'b1;
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end else if (s_desc_addr_q[3:0] != 4'b0000 || s_desc_addr_q[11:0] >= 12'hFF0) begin
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s_fault_d = 1'b1;
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s_err_sticky_d = 1'b1;
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s_err_code_d = 8'h02;
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s_err_addr_d = s_desc_addr_q;
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s_state_d = Terminal;
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s_done_d = 1'b1;
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end else if (s_read_start_ready) begin
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s_burst_index_d = '0;
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s_state_d = FetchWait;
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end
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end else begin
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unique case (s_state_q)
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FetchWait: begin
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if (abort_i) begin
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s_abort_pending_d = 1'b1;
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s_fault_d = 1'b1;
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s_err_sticky_d = 1'b1;
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s_err_code_d = 8'h08;
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s_err_addr_d = s_desc_addr_q;
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end
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if (s_read_beat_valid && s_read_beat_ready) begin
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s_fetch_word_d[s_burst_index_q[1:0]] = s_read_data;
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if (s_axi_read_fault) begin
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s_fault_d = 1'b1;
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s_err_sticky_d = 1'b1;
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s_err_code_d = 8'h04;
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s_err_addr_d = s_desc_addr_q;
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end
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if (s_read_done) begin
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s_abort_pending_d = 1'b0;
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s_state_d = Validate;
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end else begin
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s_burst_index_d = s_burst_index_q + 1'b1;
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end
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end
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end
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Validate: begin
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s_desc_buffer_d = s_fetch_word_q[0];
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s_desc_count_d = s_fetch_word_q[1];
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s_desc_next_d = s_fetch_word_q[2];
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s_desc_control_d = s_fetch_word_q[3];
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s_desc_end_d = s_fetch_word_q[3][sdio_pkg::SDIO_DESC_END];
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s_desc_irq_d = s_fetch_word_q[3][sdio_pkg::SDIO_DESC_IRQ];
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s_desc_progress_d = '0;
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s_total_seen_d = s_total_seen_q + s_fetch_word_q[1];
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if (!s_fetch_word_q[3][sdio_pkg::SDIO_DESC_OWN] ||
|
|
(s_fetch_word_q[0][1:0] != 2'b00) ||
|
|
(s_fetch_word_q[1] == 32'd0) ||
|
|
(s_fetch_word_q[3][31:18] != 14'd0) ||
|
|
(s_fetch_word_q[3][sdio_pkg::SDIO_DESC_END] &&
|
|
((s_fetch_word_q[2] != 32'd0) ||
|
|
s_fetch_word_q[3][sdio_pkg::SDIO_DESC_CHAIN])) ||
|
|
(!s_fetch_word_q[3][sdio_pkg::SDIO_DESC_END] &&
|
|
(!s_fetch_word_q[3][sdio_pkg::SDIO_DESC_CHAIN] ||
|
|
(s_fetch_word_q[2][3:0] != 4'b0000) ||
|
|
(s_fetch_word_q[2][11:0] >= 12'hFF0) ||
|
|
(s_fetch_word_q[2] == 32'd0) ||
|
|
(s_desc_index_q + 1'b1 >= s_desc_limit_q))) ||
|
|
((s_total_bytes_q != 32'd0) &&
|
|
((s_total_seen_q + s_fetch_word_q[1] > s_total_bytes_q) ||
|
|
(s_fetch_word_q[3][sdio_pkg::SDIO_DESC_END] &&
|
|
(s_total_seen_q + s_fetch_word_q[1] != s_total_bytes_q)))) ||
|
|
s_fault_q) begin
|
|
s_fault_d = 1'b1;
|
|
s_err_sticky_d = 1'b1;
|
|
if (s_err_code_q == 8'd0) s_err_code_d = 8'h02;
|
|
end
|
|
s_writeback_control_d = (s_fetch_word_q[3] &
|
|
~(32'd1 << sdio_pkg::SDIO_DESC_OWN)) |
|
|
(s_fault_d ? (32'd1 << sdio_pkg::SDIO_DESC_ERROR) :
|
|
(32'd1 << sdio_pkg::SDIO_DESC_DONE));
|
|
if (!s_fetch_word_q[3][sdio_pkg::SDIO_DESC_OWN]) begin
|
|
s_state_d = Terminal;
|
|
s_done_d = 1'b1;
|
|
end else if (s_fault_d || s_abort_pending_q) begin
|
|
s_state_d = WritebackStart;
|
|
end else if (s_direction_q == sdio_pkg::SdioDataFromCard) begin
|
|
// Card-to-host consumes the stream and AXI-writes memory.
|
|
s_state_d = PayloadWriteStart;
|
|
end else begin
|
|
// Host-to-card AXI-reads memory and produces the stream.
|
|
s_state_d = PayloadReadStart;
|
|
end
|
|
end
|
|
PayloadReadStart: begin
|
|
if (abort_i) begin
|
|
s_abort_pending_d = 1'b1;
|
|
s_fault_d = 1'b1;
|
|
s_err_sticky_d = 1'b1;
|
|
s_err_code_d = 8'h08;
|
|
s_err_addr_d = s_payload_addr;
|
|
s_state_d = WritebackStart;
|
|
end else if (s_read_start_ready) begin
|
|
s_burst_beats_d = s_payload_beats;
|
|
s_burst_index_d = '0;
|
|
s_abort_pending_d = 1'b0;
|
|
s_state_d = PayloadReadWait;
|
|
end
|
|
end
|
|
PayloadReadWait: begin
|
|
if (abort_i) begin
|
|
s_abort_pending_d = 1'b1;
|
|
s_fault_d = 1'b1;
|
|
s_err_sticky_d = 1'b1;
|
|
s_err_code_d = 8'h08;
|
|
s_err_addr_d = s_payload_addr;
|
|
end
|
|
if (s_read_beat_valid && s_read_beat_ready) begin
|
|
if (s_axi_read_fault) begin
|
|
s_fault_d = 1'b1;
|
|
s_err_sticky_d = 1'b1;
|
|
s_err_code_d = 8'h04;
|
|
s_err_addr_d = s_payload_addr + s_burst_offset;
|
|
end
|
|
if (!s_abort_pending_q && !abort_i && !s_axi_read_fault) begin
|
|
s_desc_progress_d = s_progress_after_beat;
|
|
s_total_done_d = s_total_done_q + {29'd0, s_beat_bytes};
|
|
end
|
|
if (s_read_done) begin
|
|
s_abort_pending_d = 1'b0;
|
|
if (s_fault_d || abort_i || s_abort_pending_q) begin
|
|
s_writeback_control_d = (s_desc_control_q &
|
|
~(32'd1 << sdio_pkg::SDIO_DESC_OWN)) |
|
|
(32'd1 << sdio_pkg::SDIO_DESC_ERROR);
|
|
s_state_d = WritebackStart;
|
|
end else if (s_progress_after_beat >= s_desc_count_q) begin
|
|
s_writeback_control_d = (s_desc_control_q &
|
|
~(32'd1 << sdio_pkg::SDIO_DESC_OWN)) |
|
|
(32'd1 << sdio_pkg::SDIO_DESC_DONE);
|
|
s_state_d = WritebackStart;
|
|
end else begin
|
|
s_state_d = PayloadReadStart;
|
|
end
|
|
end else begin
|
|
s_burst_index_d = s_burst_index_q + 1'b1;
|
|
end
|
|
end
|
|
end
|
|
PayloadWriteStart: begin
|
|
if (abort_i) begin
|
|
s_abort_pending_d = 1'b1;
|
|
s_fault_d = 1'b1;
|
|
s_err_sticky_d = 1'b1;
|
|
s_err_code_d = 8'h08;
|
|
s_err_addr_d = s_payload_addr;
|
|
s_writeback_control_d = (s_desc_control_q &
|
|
~(32'd1 << sdio_pkg::SDIO_DESC_OWN)) |
|
|
(32'd1 << sdio_pkg::SDIO_DESC_ERROR);
|
|
s_state_d = WritebackStart;
|
|
end else if (s_write_start_ready) begin
|
|
s_burst_beats_d = s_payload_beats;
|
|
s_burst_index_d = '0;
|
|
s_write_beat_count_d = '0;
|
|
s_write_final_sent_d = 1'b0;
|
|
s_state_d = PayloadWriteWait;
|
|
end
|
|
end
|
|
PayloadWriteWait: begin
|
|
if (abort_i) begin
|
|
s_abort_pending_d = 1'b1;
|
|
s_fault_d = 1'b1;
|
|
s_err_sticky_d = 1'b1;
|
|
s_err_code_d = 8'h08;
|
|
s_err_addr_d = s_payload_addr + s_burst_offset;
|
|
end
|
|
if (s_write_data_valid && s_write_data_ready) begin
|
|
if (!s_abort_pending_q && !abort_i) begin
|
|
if (!strobe_valid(
|
|
data_in_strb_i
|
|
) || (s_input_bytes != s_beat_bytes) ||
|
|
(data_in_last_i !=
|
|
(s_desc_end_q && (s_progress_after_beat >= s_desc_count_q)))) begin
|
|
s_fault_d = 1'b1;
|
|
s_err_sticky_d = 1'b1;
|
|
s_err_code_d = 8'h10;
|
|
end
|
|
s_desc_progress_d = s_progress_after_beat;
|
|
s_total_done_d = s_total_done_q + {29'd0, s_beat_bytes};
|
|
end
|
|
s_write_beat_count_d = s_write_beat_count_q + 1'b1;
|
|
s_burst_index_d = s_burst_index_q + 1'b1;
|
|
if (s_write_beat_count_q + 1'b1 >= s_burst_beats_q) begin
|
|
s_write_final_sent_d = 1'b1;
|
|
end
|
|
end
|
|
if (s_write_done) begin
|
|
if (s_axi_write_fault) begin
|
|
s_fault_d = 1'b1;
|
|
s_err_sticky_d = 1'b1;
|
|
s_err_code_d = 8'h04;
|
|
s_err_addr_d = s_payload_addr + s_burst_offset;
|
|
end
|
|
if (s_write_final_sent_q) begin
|
|
// A retired AXI burst is not necessarily the whole descriptor.
|
|
// Keep ownership while subsequent bursts receive its remaining
|
|
// bytes, just as the memory-to-card direction does.
|
|
if (s_fault_d || (s_desc_progress_d >= s_desc_count_q)) begin
|
|
s_writeback_control_d = (s_desc_control_q &
|
|
~(32'd1 << sdio_pkg::SDIO_DESC_OWN)) |
|
|
(s_fault_d ? (32'd1 << sdio_pkg::SDIO_DESC_ERROR) :
|
|
(32'd1 << sdio_pkg::SDIO_DESC_DONE));
|
|
s_state_d = WritebackStart;
|
|
end else begin
|
|
s_state_d = PayloadWriteStart;
|
|
end
|
|
end
|
|
end
|
|
end
|
|
WritebackStart: begin
|
|
if (s_write_start_ready) begin
|
|
s_state_d = WritebackWait;
|
|
end
|
|
end
|
|
WritebackWait: begin
|
|
if (s_write_done) begin
|
|
if (s_axi_write_fault) begin
|
|
s_fault_d = 1'b1;
|
|
s_err_sticky_d = 1'b1;
|
|
s_err_code_d = 8'h04;
|
|
s_err_addr_d = s_desc_addr_q + 32'd12;
|
|
end
|
|
if (s_fault_q || s_fault_d || s_axi_write_fault ||
|
|
s_writeback_control_q[sdio_pkg::SDIO_DESC_ERROR]) begin
|
|
s_abort_done_d = s_abort_pending_q ||
|
|
(s_writeback_control_q[sdio_pkg::SDIO_DESC_ERROR] &&
|
|
(s_err_code_q == 8'h08));
|
|
s_state_d = Terminal;
|
|
s_done_d = 1'b1;
|
|
end else if (s_desc_end_q) begin
|
|
s_descriptor_irq_d = s_desc_irq_q;
|
|
s_state_d = Terminal;
|
|
s_done_d = 1'b1;
|
|
end else begin
|
|
s_descriptor_irq_d = s_desc_irq_q;
|
|
s_desc_index_d = s_desc_index_q + 1'b1;
|
|
s_desc_addr_d = s_desc_next_q;
|
|
s_state_d = FetchStart;
|
|
end
|
|
end
|
|
end
|
|
Terminal: begin
|
|
s_state_d = Idle;
|
|
end
|
|
default: begin
|
|
s_state_d = Idle;
|
|
s_fault_d = 1'b1;
|
|
s_err_sticky_d = 1'b1;
|
|
s_err_code_d = 8'h80;
|
|
end
|
|
endcase
|
|
end
|
|
end
|
|
|
|
always_ff @(posedge clk_i or negedge rst_n_i) begin
|
|
if (!rst_n_i) begin
|
|
s_state_q <= Idle;
|
|
s_desc_addr_q <= '0;
|
|
s_desc_limit_q <= '0;
|
|
s_desc_index_q <= '0;
|
|
s_direction_q <= sdio_pkg::SdioDataFromCard;
|
|
s_total_bytes_q <= '0;
|
|
s_total_seen_q <= '0;
|
|
s_total_done_q <= '0;
|
|
s_desc_progress_q <= '0;
|
|
s_burst_beats_q <= '0;
|
|
s_burst_index_q <= '0;
|
|
s_desc_buffer_q <= '0;
|
|
s_desc_count_q <= '0;
|
|
s_desc_next_q <= '0;
|
|
s_desc_control_q <= '0;
|
|
s_writeback_control_q <= '0;
|
|
s_desc_end_q <= 1'b0;
|
|
s_desc_irq_q <= 1'b0;
|
|
s_fault_q <= 1'b0;
|
|
s_err_code_q <= '0;
|
|
s_err_addr_q <= '0;
|
|
s_done_q <= 1'b0;
|
|
s_err_sticky_q <= 1'b0;
|
|
s_abort_pending_q <= 1'b0;
|
|
s_write_final_sent_q <= 1'b0;
|
|
s_write_beat_count_q <= '0;
|
|
s_descriptor_irq_q <= 1'b0;
|
|
s_abort_done_q <= 1'b0;
|
|
for (int index = 0; index < 4; index++) begin
|
|
s_fetch_word_q[index] <= '0;
|
|
end
|
|
end else begin
|
|
s_state_q <= s_state_d;
|
|
s_desc_addr_q <= s_desc_addr_d;
|
|
s_desc_limit_q <= s_desc_limit_d;
|
|
s_desc_index_q <= s_desc_index_d;
|
|
s_direction_q <= s_direction_d;
|
|
s_total_bytes_q <= s_total_bytes_d;
|
|
s_total_seen_q <= s_total_seen_d;
|
|
s_total_done_q <= s_total_done_d;
|
|
s_desc_progress_q <= s_desc_progress_d;
|
|
s_burst_beats_q <= s_burst_beats_d;
|
|
s_burst_index_q <= s_burst_index_d;
|
|
s_desc_buffer_q <= s_desc_buffer_d;
|
|
s_desc_count_q <= s_desc_count_d;
|
|
s_desc_next_q <= s_desc_next_d;
|
|
s_desc_control_q <= s_desc_control_d;
|
|
s_writeback_control_q <= s_writeback_control_d;
|
|
s_desc_end_q <= s_desc_end_d;
|
|
s_desc_irq_q <= s_desc_irq_d;
|
|
s_fault_q <= s_fault_d;
|
|
s_err_code_q <= s_err_code_d;
|
|
s_err_addr_q <= s_err_addr_d;
|
|
s_done_q <= s_done_d;
|
|
s_err_sticky_q <= s_err_sticky_d;
|
|
s_abort_pending_q <= s_abort_pending_d;
|
|
s_write_final_sent_q <= s_write_final_sent_d;
|
|
s_write_beat_count_q <= s_write_beat_count_d;
|
|
s_descriptor_irq_q <= s_descriptor_irq_d;
|
|
s_abort_done_q <= s_abort_done_d;
|
|
for (int index = 0; index < 4; index++) begin
|
|
s_fetch_word_q[index] <= s_fetch_word_d[index];
|
|
end
|
|
end
|
|
end
|
|
|
|
`ifndef SYNTHESIS
|
|
initial begin
|
|
if ((AddrWidth < 4) || (DataWidth != 32) || (DescCount < 1) || (DescCount > 65535)) begin
|
|
$fatal(1, "sdio_dma: unsupported geometry");
|
|
end
|
|
end
|
|
`endif
|
|
endmodule
|