mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
1b69bffe4e
- Eliminated the HAVE_DEBUG preprocessor directive and all associated code from the RTL and test files. - Updated the Emulator class to remove JTAG-related debug signals and configurations. - Adjusted the pin map and JSON configurations to exclude debug-related entries. - Modified the management core wrapper to only support the HAZARD3 core, removing references to the PICORV32 core. - Updated tests to reflect the removal of the HAVE_DEBUG feature, ensuring they no longer check for debug-related conditions. - Cleaned up various scripts and makefiles to remove dependencies on the HAVE_DEBUG flag, streamlining the build process.
136 lines
6.0 KiB
Makefile
136 lines
6.0 KiB
Makefile
BUILD_DIR := $(SIM_BUILD_ROOT)
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RTL_LINT_DIR := $(VARIANT_ROOT)/lint/verilator
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SOC_CSRC_HOME += $(RTL_PATH)/dv/verilator/csrc
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SOC_CSRC_LIB_HOME += $(RTL_PATH)/dv/verilator/csrc
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SOC_CXXFILES += $(sort $(wildcard $(SOC_CSRC_HOME)/*.cpp))
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SOC_CSRC_INCLPATH += -I$(SOC_CSRC_HOME)
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SOC_CSRC_INCLPATH += $(foreach val, $(SOC_CSRC_LIB_HOME), -I$(val))
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SOC_VSRC_TOP := retrosoc_top
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SOC_VSRC_HOME += $(RTL_PATH)/dv/verilator/rtl
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SOC_COMPILE_HOME := $(BUILD_DIR)/emu_compile
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SOC_VXXFILES := $(RTL_FLIST)
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SOC_VXXFILES += $(RTL_PATH)/dv/model/ESP_PSRAM64H.sv
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SOC_VXXFILES += $(RTL_PATH)/dv/verilator/rtl/flash_read_binder.sv
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SOC_VXXFILES += $(RTL_PATH)/dv/verilator/rtl/QSPIFlash.sv
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SOC_VXXFILES += $(RTL_PATH)/dv/verilator/rtl/retrosoc_top.sv
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SOC_VXXFILES += $(RTL_PATH)/dv/verilator/rtl/sdram_verilator_model.sv
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SOC_VSRC_INCLPATH += -I$(SOC_VSRC_HOME)
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VERILATOR ?= verilator
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VERILATOR_JOBS ?= $(JOBS)
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VERILATOR_CXXFLAGS += -std=c++17 -Wall $(SOC_CSRC_INCLPATH) -DDUMP_WAVE_FST
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VERILATOR_FLAGS += --cc --exe --no-timing --top-module $(SOC_VSRC_TOP)
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VERILATOR_FLAGS += --x-assign unique -O3 -CFLAGS "$(VERILATOR_CXXFLAGS)"
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VERILATOR_FLAGS += --trace-fst --assert --stats-vars --output-split 30000 --output-split-cfuncs 30000
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VERILATOR_FLAGS += --timescale "1ns/1ns" -Wno-fatal
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VERILATOR_FLAGS += -o $(BUILD_DIR)/emu
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VERILATOR_FLAGS += -Mdir $(SOC_COMPILE_HOME)
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VERILATOR_FLAGS += $(SOC_VSRC_INCLPATH) $(SOC_CXXFILES) $(SOC_VXXFILES)
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RTL_LINT_FLAGS := --lint-only --no-timing --top-module $(SOC_VSRC_TOP)
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RTL_LINT_FLAGS += --assert --Wall --timescale "1ns/1ns" -Wno-fatal
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RTL_LINT_FLAGS += $(SOC_VSRC_INCLPATH) $(SOC_VXXFILES)
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SOC_SIM_TIME ?= 180
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OPENOCD ?= openocd
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RISCV_GDB ?= riscv32-unknown-elf-gdb
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DEBUG_SIM_DIR := $(SIM_BUILD_ROOT)/debug
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DEBUG_OPENOCD_CONFIG := $(RTL_PATH)/dv/verilator/openocd/retrosoc_hazard3.cfg
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DEBUG_SIM_SESSION := $(ROOT_PATH)/scripts/run_debug_session.py
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VERILATOR_STAMP := $(BUILD_DIR)/verilate.stamp
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VERILATOR_DEPFILE := $(BUILD_DIR)/verilate.d
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VERILATOR_EMU := $(BUILD_DIR)/emu
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RTL_LINT_STAMP := $(RTL_LINT_DIR)/rtl-lint.stamp
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RTL_LINT_DEPFILE := $(RTL_LINT_DIR)/rtl-lint.d
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VERILATOR_EXTRA_SOURCES := $(RTL_PATH)/dv/model/ESP_PSRAM64H.sv \
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$(RTL_PATH)/dv/verilator/rtl/flash_read_binder.sv \
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$(RTL_PATH)/dv/verilator/rtl/QSPIFlash.sv \
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$(RTL_PATH)/dv/verilator/rtl/retrosoc_top.sv \
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$(RTL_PATH)/dv/verilator/rtl/sdram_verilator_model.sv \
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$(SOC_CXXFILES) $(wildcard $(SOC_CSRC_HOME)/*.h) \
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$(wildcard $(SOC_CSRC_HOME)/*.hpp)
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-include $(VERILATOR_DEPFILE) $(RTL_LINT_DEPFILE)
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CCACHE := $(shell command -v ccache 2>/dev/null)
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ifneq ($(CCACHE),)
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export OBJCACHE = ccache
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export CCACHE_DIR = $(CACHE_ROOT)/ccache/verilator
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export CCACHE_TEMPDIR = $(CACHE_ROOT)/ccache/verilator/tmp
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endif
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$(VERILATOR_STAMP): $(MPW_VARIANT_STAMP) $(FILELIST_STAMP) $(VERILATOR_EXTRA_SOURCES)
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@mkdir -p $(BUILD_DIR)
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@mkdir -p $(CCACHE_TEMPDIR)
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python3 $(ROOT_PATH)/scripts/run_flow.py --tool verilator \
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--log $(BUILD_DIR)/verilating.log --result $(BUILD_DIR)/result-verilate.json \
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-- $(VERILATOR) $(VERILATOR_FLAGS)
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python3 $(RTL_PATH)/script/filelist_deps.py $(RTL_FLIST) \
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$(foreach source,$(VERILATOR_EXTRA_SOURCES),--extra $(source)) \
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--target $@ --output $(VERILATOR_DEPFILE)
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@touch $@
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$(VERILATOR_EMU): $(VERILATOR_STAMP)
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python3 $(ROOT_PATH)/scripts/run_flow.py --tool verilator-compile \
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--log $(BUILD_DIR)/compile.log --result $(BUILD_DIR)/result-compile.json \
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-- make -j$(VERILATOR_JOBS) VM_PARALLEL_BUILDS=1 OPT_FAST=-O3 -C $(SOC_COMPILE_HOME) \
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-f V$(SOC_VSRC_TOP).mk
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$(RTL_LINT_STAMP): $(MPW_VARIANT_STAMP) $(FILELIST_STAMP) $(VERILATOR_EXTRA_SOURCES)
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@mkdir -p $(RTL_LINT_DIR)
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python3 $(ROOT_PATH)/scripts/run_flow.py --tool rtl-lint \
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--log $(RTL_LINT_DIR)/lint.log --result $(RTL_LINT_DIR)/result-rtl-lint.json \
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-- $(VERILATOR) $(RTL_LINT_FLAGS)
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python3 $(RTL_PATH)/script/filelist_deps.py $(RTL_FLIST) \
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$(foreach source,$(VERILATOR_EXTRA_SOURCES),--extra $(source)) \
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--target $@ --output $(RTL_LINT_DEPFILE)
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@touch $@
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rtl-lint: $(RTL_LINT_STAMP) | manifest
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check-rtl-lint: rtl-lint
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python3 $(ROOT_PATH)/scripts/analyze_warnings.py check --root $(ROOT_PATH) \
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--profile $(PROFILE_NAME) --variant-root $(VARIANT_ROOT) --tool rtl-lint \
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--output $(META_DIR)/rtl-lint-warnings.json
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lint: rtl-lint
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comp: $(VERILATOR_EMU)
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sim: comp
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@test -f $(SW_BUILD_DIR)/$(SIM_FIRMWARE_NAME).bin || { \
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echo "firmware image missing; run 'make firmware' first" >&2; exit 1; }
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python3 $(ROOT_PATH)/scripts/run_flow.py --tool verilator-sim --stream-bytes \
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--log $(BUILD_DIR)/sim.log --result $(BUILD_DIR)/result-sim.json \
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--cwd $(BUILD_DIR) -- $(BUILD_DIR)/emu -i $(SW_BUILD_DIR)/$(SIM_FIRMWARE_NAME).bin \
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-t $(SOC_SIM_TIME)
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python3 $(ROOT_PATH)/scripts/check_simulation.py --log $(BUILD_DIR)/sim.log \
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--result $(BUILD_DIR)/result-sim-check.json --require '$(SIM_SUCCESS_MARKER)'
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debug-sim: comp firmware
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@test "$(SIMU)" = VERILATOR || { echo "debug-sim requires SIMU=VERILATOR" >&2; exit 2; }
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$(FLOW_PYTHON) $(ROOT_PATH)/scripts/doctor.py --root $(ROOT_PATH) --simu $(SIMU) \
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--synth $(SYNTH) --sta $(STA) --pdk $(PDK) --formal $(FORMAL) \
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--require-debug-tools --lock $(LOCK_FILE)
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python3 $(DEBUG_SIM_SESSION) \
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--emulator $(VERILATOR_EMU) \
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--image $(SW_BUILD_DIR)/$(FIRMWARE_NAME).bin \
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--elf $(SW_BUILD_DIR)/firmware \
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--openocd $(OPENOCD) \
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--gdb $(RISCV_GDB) \
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--openocd-config $(DEBUG_OPENOCD_CONFIG) \
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--log-dir $(DEBUG_SIM_DIR) \
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--result $(DEBUG_SIM_DIR)/result-debug-sim.json \
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--timeout $(SOC_SIM_TIME) \
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--sim-time $(SOC_SIM_TIME)
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comp sim: | manifest
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wave:
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clean:
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python3 $(ROOT_PATH)/scripts/clean.py --root $(ROOT_PATH) --path $(BUILD_DIR)
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python3 $(ROOT_PATH)/scripts/clean.py --root $(ROOT_PATH) --path $(RTL_LINT_DIR)
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.PHONY: lint rtl-lint check-rtl-lint comp sim debug-sim clean |