mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
24d425c3e8
- Updated formal.mk to include PSRAM in formal verification targets and source files. - Modified software.mk to include psram_math.c for HAL. - Enhanced pin_map.json to map GPIO pins for PSRAM control signals. - Refactored ip_ribp_wrapper.sv to integrate PSRAM interface and remove unused ribp interfaces. - Updated rtl_style_audit.json to include PSRAM related files. - Added PSRAM testbench (psram_tb.sv) for integration testing. - Created test_psram.py to validate PSRAM controller functionality and register offsets. - Adjusted memory map tests to reflect new PSRAM address space and size.
168 lines
13 KiB
C
168 lines
13 KiB
C
#ifndef _RETROSOC_DEF_H_
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#define _RETROSOC_DEF_H_
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#include <stdint.h>
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#include <stdbool.h>
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#include <retrosoc/generated/memory_map.h>
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#include <retrosoc/generated/user_extensions.h>
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#define HW_CORE "Management Hazard3"
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#define CPU_FREQ 72 // unit: MHz
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#define UART_BPS 921600 // unit: bps
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#define SPFS_MEM_START RS_SOC_FLASH_BASE
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#define SPFS_MEM_OFFST RS_SOC_FLASH_SIZE
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#define SRAM_MEM_START RS_SOC_SRAM_BASE
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#define SRAM_MEM_OFFST RS_SOC_SRAM_SIZE
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#define SDRAM_MEM_START RS_SOC_SDRAM_BASE
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#define SDRAM_MEM_OFFST RS_SOC_SDRAM_SIZE
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#define PSRAM_MEM_START RS_SOC_PSRAM_BASE
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#define PSRAM_MEM_OFFST RS_SOC_PSRAM_SIZE
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#define XPI_MEM_START RS_SOC_XPI_BASE
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#define XPI_MEM_OFFST RS_SOC_XPI_SIZE
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#define TF_CARD_START RS_SOC_SPISD_BASE
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#define TF_CARD_OFFST RS_SOC_SPISD_SIZE
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#define RS_SOC_REG32(base, offset) (*(volatile uint32_t *)(uintptr_t)((base) + (offset)))
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// spisd
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#define reg_spisd_mode RS_SOC_REG32(RS_SOC_RIBP_SPISD_BASE, UINT32_C(0x00))
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#define reg_spisd_clkdiv RS_SOC_REG32(RS_SOC_RIBP_SPISD_BASE, UINT32_C(0x04))
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#define reg_spisd_addr RS_SOC_REG32(RS_SOC_RIBP_SPISD_BASE, UINT32_C(0x08))
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#define reg_spisd_txdata RS_SOC_REG32(RS_SOC_RIBP_SPISD_BASE, UINT32_C(0x0C))
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#define reg_spisd_rxdata RS_SOC_REG32(RS_SOC_RIBP_SPISD_BASE, UINT32_C(0x10))
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#define reg_spisd_status RS_SOC_REG32(RS_SOC_RIBP_SPISD_BASE, UINT32_C(0x14))
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#define reg_spisd_sync RS_SOC_REG32(RS_SOC_RIBP_SPISD_BASE, UINT32_C(0x18))
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// i2s
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#define reg_i2s_mode RS_SOC_REG32(RS_SOC_RIBP_I2S_BASE, UINT32_C(0x00))
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#define reg_i2s_format RS_SOC_REG32(RS_SOC_RIBP_I2S_BASE, UINT32_C(0x04))
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#define reg_i2s_upbound RS_SOC_REG32(RS_SOC_RIBP_I2S_BASE, UINT32_C(0x08))
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#define reg_i2s_lowbound RS_SOC_REG32(RS_SOC_RIBP_I2S_BASE, UINT32_C(0x0C))
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#define reg_i2s_recven RS_SOC_REG32(RS_SOC_RIBP_I2S_BASE, UINT32_C(0x10))
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#define reg_i2s_txdata RS_SOC_REG32(RS_SOC_RIBP_I2S_BASE, UINT32_C(0x14))
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#define reg_i2s_rxdata RS_SOC_REG32(RS_SOC_RIBP_I2S_BASE, UINT32_C(0x18))
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#define reg_i2s_status RS_SOC_REG32(RS_SOC_RIBP_I2S_BASE, UINT32_C(0x1C))
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#define reg_i2s_stream_ctrl RS_SOC_REG32(RS_SOC_RIBP_I2S_BASE, UINT32_C(0x20))
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// xpi
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#define reg_xpi_cfgidx RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x00))
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#define reg_xpi_accmd RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x04))
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#define reg_xpi_mmstad RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x08))
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#define reg_xpi_mmoffst RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x0C))
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#define reg_xpi_mode RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x10))
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#define reg_xpi_nss RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x14))
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#define reg_xpi_clkdiv RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x18))
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#define reg_xpi_rdwr RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x1C))
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#define reg_xpi_revdat RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x20))
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#define reg_xpi_txupb RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x24))
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#define reg_xpi_txlowb RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x28))
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#define reg_xpi_rxupb RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x2C))
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#define reg_xpi_rxlowb RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x30))
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#define reg_xpi_flush RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x34))
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#define reg_xpi_cmdtyp RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x38))
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#define reg_xpi_cmdlen RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x3C))
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#define reg_xpi_cmddat RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x40))
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#define reg_xpi_adrtyp RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x44))
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#define reg_xpi_adrlen RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x48))
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#define reg_xpi_adrdat RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x4C))
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#define reg_xpi_alttyp RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x50))
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#define reg_xpi_altlen RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x54))
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#define reg_xpi_altdat RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x58))
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#define reg_xpi_tdulen RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x5C))
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#define reg_xpi_rdulen RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x60))
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#define reg_xpi_dattyp RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x64))
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#define reg_xpi_datlen RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x68))
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#define reg_xpi_datbit RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x6C))
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#define reg_xpi_hlvlen RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x70))
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#define reg_xpi_txdata RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x74))
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#define reg_xpi_rxdata RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x78))
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#define reg_xpi_start RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x7C))
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#define reg_xpi_status RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x80))
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// dma(32b xfer, hardware trigger by I2S fifo, QSPI fifo)
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#define reg_dma_mode RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x00))
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#define reg_dma_srcaddr RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x04))
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#define reg_dma_srcincr RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x08))
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#define reg_dma_dstaddr RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x0C))
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#define reg_dma_dstincr RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x10))
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#define reg_dma_xferlen RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x14))
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#define reg_dma_start RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x18))
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#define reg_dma_stop RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x1C))
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#define reg_dma_reset RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x20))
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#define reg_dma_status RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x24))
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#define reg_dma_fsm RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x28))
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#define reg_dma_error_status RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x2C))
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#define reg_dma_error_addr RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x30))
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#define RS_SOC_DMA_ERROR_PENDING UINT32_C(0x00000001)
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#define RS_SOC_DMA_ERROR_RESPONSE_SHIFT 1U
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#define RS_SOC_DMA_ERROR_RESPONSE_MASK UINT32_C(0x0000000E)
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// sys ctrl
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#define RS_SOC_SYSCTRL_REG32(offset) RS_SOC_REG32(RS_SOC_RIBP_SYSCTRL_BASE, (offset))
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#define reg_sysctrl_coresel RS_SOC_REG32(RS_SOC_RIBP_SYSCTRL_BASE, UINT32_C(0x00))
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#define reg_sysctrl_ipsel RS_SOC_REG32(RS_SOC_RIBP_SYSCTRL_BASE, UINT32_C(0x04))
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#define reg_sysctrl_pll_cfg RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PLL_CFG_OFFSET)
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#define reg_sysctrl_pll_cmd RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PLL_CMD_OFFSET)
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/* Status: bit 0 pending (W1C), bit 1 write, bits 3:2 reason (1 unmapped, 2 reserved). */
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#define reg_sysctrl_bus_fault_status RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_FAULT_STATUS_OFFSET)
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#define reg_sysctrl_bus_fault_addr RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_FAULT_ADDR_OFFSET)
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#define reg_sysctrl_bus_fault_count RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_FAULT_COUNT_OFFSET)
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#define reg_sysctrl_pll_status RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PLL_STATUS_OFFSET)
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#define reg_sysctrl_user_core_reset RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_USER_CORE_RESET_OFFSET)
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#define reg_sysctrl_user_core_status RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_USER_CORE_STATUS_OFFSET)
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#define reg_sysctrl_bus_fault_master RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_FAULT_MASTER_OFFSET)
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#define reg_sysctrl_bus_fault_detail RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_FAULT_DETAIL_OFFSET)
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#define reg_sysctrl_perf_ctrl RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_CTRL_OFFSET)
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#define reg_sysctrl_perf_mgmt_wait_lo RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_MGMT_WAIT_LO_OFFSET)
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#define reg_sysctrl_perf_mgmt_wait_hi RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_MGMT_WAIT_HI_OFFSET)
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#define reg_sysctrl_perf_user_wait_lo RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_USER_WAIT_LO_OFFSET)
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#define reg_sysctrl_perf_user_wait_hi RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_USER_WAIT_HI_OFFSET)
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#define reg_sysctrl_perf_dma_wait_lo RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_DMA_WAIT_LO_OFFSET)
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#define reg_sysctrl_perf_dma_wait_hi RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_DMA_WAIT_HI_OFFSET)
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#define reg_sysctrl_perf_ribp_wait_lo RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_RIBP_WAIT_LO_OFFSET)
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#define reg_sysctrl_perf_ribp_wait_hi RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_RIBP_WAIT_HI_OFFSET)
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#define reg_sysctrl_perf_apb_wait_lo RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_APB_WAIT_LO_OFFSET)
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#define reg_sysctrl_perf_apb_wait_hi RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_APB_WAIT_HI_OFFSET)
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#define reg_sysctrl_perf_sdram_wait_lo \
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RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_SDRAM_WAIT_LO_OFFSET)
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#define reg_sysctrl_perf_sdram_wait_hi \
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RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_SDRAM_WAIT_HI_OFFSET)
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#define reg_sysctrl_perf_psram_wait_lo \
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RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_PSRAM_WAIT_LO_OFFSET)
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#define reg_sysctrl_perf_psram_wait_hi \
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RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_PSRAM_WAIT_HI_OFFSET)
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#define reg_sysctrl_perf_flash_wait_lo \
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RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_FLASH_WAIT_LO_OFFSET)
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#define reg_sysctrl_perf_flash_wait_hi \
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RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_FLASH_WAIT_HI_OFFSET)
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#define reg_sysctrl_test_status RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_TEST_STATUS_OFFSET)
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#define reg_sysctrl_rtc_wake_status RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_RTC_WAKE_STATUS_OFFSET)
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#define RS_SOC_TEST_STATUS_VALID UINT32_C(0x80000000)
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#define RS_SOC_TEST_STATUS_CODE_SHIFT 8U
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#define RS_SOC_TEST_STATUS_PASS UINT32_C(0x00000001)
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#define RS_SOC_BUS_FAULT_PENDING UINT32_C(0x00000001)
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#define RS_SOC_BUS_FAULT_WRITE UINT32_C(0x00000002)
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#define RS_SOC_BUS_FAULT_REASON_MASK UINT32_C(0x0000000C)
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#define RS_SOC_BUS_FAULT_REASON_UNMAPPED UINT32_C(0x00000004)
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#define RS_SOC_BUS_FAULT_REASON_RESERVED UINT32_C(0x00000008)
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#define RS_SOC_BUS_FAULT_RESPONSE_OK UINT32_C(0x00000000)
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#define RS_SOC_BUS_FAULT_RESPONSE_DECERR UINT32_C(0x00000001)
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#define RS_SOC_BUS_FAULT_RESPONSE_PROTERR UINT32_C(0x00000002)
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#define RS_SOC_BUS_FAULT_RESPONSE_SLVERR UINT32_C(0x00000003)
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#define RS_SOC_BUS_FAULT_RESPONSE_TIMEOUT UINT32_C(0x00000004)
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#define RS_SOC_BUS_FAULT_RESPONSE_RESERVED UINT32_C(0x00000005)
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#define RS_SOC_PERF_CTRL_ENABLE UINT32_C(0x00000001)
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#define RS_SOC_PERF_CTRL_CLEAR UINT32_C(0x00000002)
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#define RS_SOC_PERF_CTRL_SNAPSHOT UINT32_C(0x00000004)
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#define RS_SOC_RTC_WAKE_LIVE UINT32_C(0x00000001)
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#define RS_SOC_RTC_WAKE_SEEN UINT32_C(0x00000002)
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// sdram
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#define reg_sdram_clkdiv RS_SOC_REG32(RS_SOC_RIBP_SDRAM_BASE, UINT32_C(0x00))
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#define reg_sdram_cfg RS_SOC_REG32(RS_SOC_RIBP_SDRAM_BASE, UINT32_C(0x04))
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#define reg_user_ip_reg0 RS_SOC_REG32(RS_SOC_APB_USER_IP_BASE, UINT32_C(0x00))
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#define reg_user_ip_reg1 RS_SOC_REG32(RS_SOC_APB_USER_IP_BASE, UINT32_C(0x04))
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#define reg_user_ip_reg2 RS_SOC_REG32(RS_SOC_APB_USER_IP_BASE, UINT32_C(0x08))
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#define reg_user_ip_reg3 RS_SOC_REG32(RS_SOC_APB_USER_IP_BASE, UINT32_C(0x0C))
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#define reg_user_ip_reg4 RS_SOC_REG32(RS_SOC_APB_USER_IP_BASE, UINT32_C(0x10))
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#define reg_user_ip_reg5 RS_SOC_REG32(RS_SOC_APB_USER_IP_BASE, UINT32_C(0x14))
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#define reg_user_ip_reg6 RS_SOC_REG32(RS_SOC_APB_USER_IP_BASE, UINT32_C(0x18))
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#endif
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