mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
24d425c3e8
- Updated formal.mk to include PSRAM in formal verification targets and source files. - Modified software.mk to include psram_math.c for HAL. - Enhanced pin_map.json to map GPIO pins for PSRAM control signals. - Refactored ip_ribp_wrapper.sv to integrate PSRAM interface and remove unused ribp interfaces. - Updated rtl_style_audit.json to include PSRAM related files. - Added PSRAM testbench (psram_tb.sv) for integration testing. - Created test_psram.py to validate PSRAM controller functionality and register offsets. - Adjusted memory map tests to reflect new PSRAM address space and size.
324 lines
10 KiB
Systemverilog
324 lines
10 KiB
Systemverilog
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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`include "mmap_define.svh"
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`include "soc_irq_config.svh"
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`include "rib_defs.svh"
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module ip_ribp_wrapper (
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// verilog_format: off -- preserve reviewed column alignment
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input logic clk_i,
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input logic rst_n_i,
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input logic clk_aud_i,
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input logic rst_aud_n_i,
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input logic debug_halted_i,
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input logic timebase_tick_i,
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axi4_if.slave cfg_axi4,
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axi4_if.slave psram_axi4,
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axi4_if.slave xpi_axi4,
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axi4_if.slave spisd_axi4,
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gpio_if.dut gpio,
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user_gpio_if.padctrl user_gpio,
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uart_if.dut uart,
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psram_if.dut psram,
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spi_if.dut spisd,
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i2c_if.dut i2c0,
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i2s_if.dut i2s,
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ws2812_if.dut ws2812,
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xpi_if.dut xpi,
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axi4_if.master dma_axi4,
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sysctrl_if.dut sysctrl,
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pll_ctrl_if.sysctrl pll_ctrl,
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ribp_if.master sdram_cfg_ribp,
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dvp_if.dut dvp,
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sdio_if.dut sdio,
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opipsram_if.dut opipsram,
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i2c_if.dut i2c1,
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input logic fault_valid_i,
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input logic [31:0] fault_addr_i,
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input logic [3:0] fault_wstrb_i,
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input logic fault_reserved_i,
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output logic [`SOC_IRQ_RIBP_WIDTH-1:0] irq_o
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// verilog_format: on
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);
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// verilog_format: off -- preserve reviewed column alignment
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// Generated RIBP target declarations preserve scalar-interface compatibility.
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`include "ribp_interfaces.svh"
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ribp_if ribp ();
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ribp_if u_xpi_data_ribp_if ();
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ribp_if u_xpi_target_ribp_if ();
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ribp_if u_spisd_data_ribp_if ();
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ribp_if u_spisd_target_ribp_if ();
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rib_if u_dma_rib_if ();
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axi4_stream_if #(.DATA_WIDTH(32), .ID_WIDTH(1), .DEST_WIDTH(1), .USER_WIDTH(1))
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u_i2s_tx_axis_if (.aclk(clk_i), .aresetn(rst_n_i));
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axi4_stream_if #(.DATA_WIDTH(32), .ID_WIDTH(1), .DEST_WIDTH(1), .USER_WIDTH(1))
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u_i2s_rx_axis_if (.aclk(clk_i), .aresetn(rst_n_i));
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axi4_stream_if #(.DATA_WIDTH(32), .ID_WIDTH(1), .DEST_WIDTH(1), .USER_WIDTH(1))
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u_dvp_rx_axis_if (.aclk(clk_i), .aresetn(rst_n_i));
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// verilog_format: on
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clint_if u_clint_if ();
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dma_hw_trg_if u_dma_hw_trg_if ();
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logic s_dma_i2s_tx_stall, s_dma_i2s_rx_stall;
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logic s_dma_xpi_tx_stall, s_dma_xpi_rx_stall;
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logic s_dma_uart_tx_stall, s_dma_uart_rx_stall;
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logic s_dma_i2c0_tx_stall, s_dma_i2c0_rx_stall;
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logic s_dma_i2c1_tx_stall, s_dma_i2c1_rx_stall;
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logic s_dma_xfer_done;
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logic s_tim0_irq, s_tim1_irq;
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logic s_dvp_irq;
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`ifdef PDK_GF180
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localparam bit GPIO_HAS_INPUT_CMOS = 1'b1;
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localparam bit GPIO_HAS_PULL_UP = 1'b1;
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localparam bit GPIO_HAS_PULL_DOWN = 1'b1;
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`elsif PDK_ICS55
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localparam bit GPIO_HAS_INPUT_CMOS = 1'b1;
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localparam bit GPIO_HAS_PULL_UP = 1'b1;
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localparam bit GPIO_HAS_PULL_DOWN = 1'b1;
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`elsif PDK_SKY130
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localparam bit GPIO_HAS_INPUT_CMOS = 1'b1;
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localparam bit GPIO_HAS_PULL_UP = 1'b0;
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localparam bit GPIO_HAS_PULL_DOWN = 1'b0;
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`else
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localparam bit GPIO_HAS_INPUT_CMOS = 1'b0;
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localparam bit GPIO_HAS_PULL_UP = 1'b0;
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localparam bit GPIO_HAS_PULL_DOWN = 1'b0;
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`endif
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axi42ribp u_axi42ribp (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.axi4 (cfg_axi4),
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.ribp (ribp)
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);
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axi42ribp_burst u_xpi_axi42ribp (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.axi4 (xpi_axi4),
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.ribp (u_xpi_data_ribp_if)
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);
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axi42ribp_burst u_spisd_axi42ribp (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.axi4 (spisd_axi4),
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.ribp (u_spisd_data_ribp_if)
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);
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ribp_arbiter2 u_xpi_ribp_arbiter (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.cfg (u_xpi_ribp_if),
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.data (u_xpi_data_ribp_if),
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.target (u_xpi_target_ribp_if)
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);
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ribp_arbiter2 u_spisd_ribp_arbiter (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.cfg (u_spisd_ribp_if),
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.data (u_spisd_data_ribp_if),
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.target (u_spisd_target_ribp_if)
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);
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rib2axi4 u_dma_rib2axi4 (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.rib (u_dma_rib_if),
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.axi4 (dma_axi4)
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);
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// Generated target routing operates on the RIBP configuration boundary
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// behind the AXI4 adapter. Register targets therefore remain INCR1-only.
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assign u_dma_hw_trg_if.i2s_tx_proc = ~s_dma_i2s_tx_stall;
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assign u_dma_hw_trg_if.i2s_rx_proc = ~s_dma_i2s_rx_stall;
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assign u_dma_hw_trg_if.qspi_tx_proc = ~s_dma_xpi_tx_stall;
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assign u_dma_hw_trg_if.qspi_rx_proc = ~s_dma_xpi_rx_stall;
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assign u_dma_hw_trg_if.uart_tx_proc = ~s_dma_uart_tx_stall;
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assign u_dma_hw_trg_if.uart_rx_proc = ~s_dma_uart_rx_stall;
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assign u_dma_hw_trg_if.i2c0_tx_proc = ~s_dma_i2c0_tx_stall;
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assign u_dma_hw_trg_if.i2c0_rx_proc = ~s_dma_i2c0_rx_stall;
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assign u_dma_hw_trg_if.i2c1_tx_proc = ~s_dma_i2c1_tx_stall;
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assign u_dma_hw_trg_if.i2c1_rx_proc = ~s_dma_i2c1_rx_stall;
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// Uses ClusterIP common ribp_if and register.sv dffr through generated bindings.
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`include "ribp_routes.svh"
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// verilog_format: off -- preserve reviewed column alignment
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// Generated IRQ ownership and core-vector bit assignments are topology checked.
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`include "ribp_irq_bindings.svh"
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ribp_gpio #(
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.UserBaseAddr (`SOC_ADDR_RIBP_GPIO_BASE),
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.AdminBaseAddr(`SOC_ADDR_RIBP_GPIO_ADMIN_BASE),
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.HasInputCmos (GPIO_HAS_INPUT_CMOS),
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.HasPullUp (GPIO_HAS_PULL_UP),
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.HasPullDown (GPIO_HAS_PULL_DOWN)
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) u_rib_gpio (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.ribp (u_gpio_ribp_if),
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.gpio (gpio),
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.user_gpio (user_gpio)
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);
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// verilog_format: on
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ribp_uart u_rib_uart (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.dma_tx_stall_o(s_dma_uart_tx_stall),
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.dma_rx_stall_o(s_dma_uart_rx_stall),
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.ribp (u_uart_ribp_if),
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.uart (uart)
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);
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ribp_timer u_rib_timer0 (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.debug_halted_i(debug_halted_i),
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.ribp (u_tim0_ribp_if),
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.irq_o (s_tim0_irq)
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);
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ribp_timer u_rib_timer1 (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.debug_halted_i(debug_halted_i),
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.ribp (u_tim1_ribp_if),
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.irq_o (s_tim1_irq)
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);
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ribp_psram u_rib_psram (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.cfg_ribp(u_psram_ribp_if),
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.mem_axi4(psram_axi4),
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.psram (psram)
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);
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ribp_spisd u_rib_spisd (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.ribp (u_spisd_target_ribp_if),
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.spi (spisd)
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);
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ribp_i2c u_rib_i2c0 (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.dma_tx_stall_o(s_dma_i2c0_tx_stall),
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.dma_rx_stall_o(s_dma_i2c0_rx_stall),
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.ribp (u_i2c0_ribp_if),
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.i2c (i2c0)
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);
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ribp_i2s u_rib_i2s (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.clk_aud_i (clk_aud_i),
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.rst_aud_n_i (rst_aud_n_i),
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.dma_tx_stall_o(s_dma_i2s_tx_stall),
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.dma_rx_stall_o(s_dma_i2s_rx_stall),
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.ribp (u_i2s_ribp_if),
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.tx_axis (u_i2s_tx_axis_if),
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.rx_axis (u_i2s_rx_axis_if),
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.i2s (i2s)
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);
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ribp_ws2812 u_rib_ws2812 (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.ribp (u_ws2812_ribp_if),
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.ws2812 (ws2812)
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);
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ribp_xpi u_rib_xpi (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.dma_xfer_done_i(s_dma_xfer_done),
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.dma_tx_stall_o (s_dma_xpi_tx_stall),
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.dma_rx_stall_o (s_dma_xpi_rx_stall),
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.ribp (u_xpi_target_ribp_if),
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.xpi (xpi)
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);
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ribp_dma u_rib_dma (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.dma_xfer_done_o(s_dma_xfer_done),
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.hw_trg (u_dma_hw_trg_if),
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.ribp (u_dma_ribp_if),
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.rib (u_dma_rib_if),
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.i2s_tx_axis (u_i2s_tx_axis_if),
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.i2s_rx_axis (u_i2s_rx_axis_if),
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.dvp_rx_axis (u_dvp_rx_axis_if)
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);
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ribp_sysctrl u_rib_sysctrl (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.fault_valid_i (fault_valid_i),
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.fault_addr_i (fault_addr_i),
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.fault_wstrb_i (fault_wstrb_i),
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.fault_reserved_i(fault_reserved_i),
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.ribp (u_sysctrl_ribp_if),
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.sysctrl (sysctrl),
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.pll_ctrl (pll_ctrl)
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);
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ribp_clint u_rib_clint (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.timebase_tick_i(timebase_tick_i),
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.ribp (u_clint_ribp_if),
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.clint (u_clint_if)
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);
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axi4s_dvp u_axi4_dvp (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.ribp (u_dvp_ribp_if),
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.rx_axis(u_dvp_rx_axis_if),
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.dvp (dvp),
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.irq_o (s_dvp_irq)
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);
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ribp_sdio u_rib_sdio (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.ribp (u_sdio_ribp_if),
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.sdio (sdio)
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);
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ribp_opipsram u_rib_opipsram (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.ribp (u_opipsram_ribp_if),
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.psram (opipsram)
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);
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ribp_i2c u_rib_i2c1 (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.dma_tx_stall_o(s_dma_i2c1_tx_stall),
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.dma_rx_stall_o(s_dma_i2c1_rx_stall),
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.ribp (u_i2c1_ribp_if),
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.i2c (i2c1)
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);
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endmodule
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