maksyuki 24d425c3e8 feat: add PSRAM support and related tests ...

- Updated formal.mk to include PSRAM in formal verification targets and source files.
- Modified software.mk to include psram_math.c for HAL.
- Enhanced pin_map.json to map GPIO pins for PSRAM control signals.
- Refactored ip_ribp_wrapper.sv to integrate PSRAM interface and remove unused ribp interfaces.
- Updated rtl_style_audit.json to include PSRAM related files.
- Added PSRAM testbench (psram_tb.sv) for integration testing.
- Created test_psram.py to validate PSRAM controller functionality and register offsets.
- Adjusted memory map tests to reflect new PSRAM address space and size.

2026-08-15 19:11:22 +08:00

..

apb4_if_bridge_tb.sv

feat: enhance build variant ID generation and regression environment setup

2026-07-21 10:59:31 +08:00

axi4_interconnect_tb.sv

refactor: refactor parameter naming conventions and update RTL style

2026-08-13 15:08:24 +08:00

axi42ribp_burst_tb.sv

feat: enhance AXI4 and RIBP interfaces with burst support and address generation

2026-08-13 22:37:01 +08:00

bus_fault_tb.sv

feat: add AXI4 interconnect testbench and enhance existing tests

2026-08-12 12:30:12 +08:00

clint_tb.sv

refactor: refactor parameter naming conventions and update RTL style

2026-08-13 15:08:24 +08:00

dma_error_tb.sv

feat: add AXI4 interconnect testbench and enhance existing tests

2026-08-12 12:30:12 +08:00

dvp_tb.sv

refactor: rename ribp_dvp module to axi4s_dvp for consistency across the design

2026-08-13 16:34:28 +08:00

gpio_tb.sv

refactor: refactor parameter naming conventions and update RTL style

2026-08-13 15:08:24 +08:00

i2c_tb.sv

refactor: refactor RTL paths and update test descriptions

2026-08-13 13:41:52 +08:00

mgmt_debug_reset_tb.sv

feat: add management debug reset and JTAG integration for Hazard3

2026-08-05 22:30:11 +08:00

pll_ctrl_tb.sv

feat: add watchdog (wdg) module integration and update related components

2026-08-10 22:26:33 +08:00

psram_tb.sv

feat: add PSRAM support and related tests

2026-08-15 19:11:22 +08:00

rib2apb_tb.sv

feat: refactor UART and Timer Interfaces; Remove Unused Components

2026-08-11 09:02:35 +08:00

rib2ram_tb.sv

feat: refactor RIB interfaces and update test cases

2026-08-04 16:12:22 +08:00

rib_bus_tb.sv

feat: add AXI4 interconnect testbench and enhance existing tests

2026-08-12 12:30:12 +08:00

ribp_topology_tb.sv

feat: enhance AXI4 and RIBP interfaces with burst support and address generation

2026-08-13 22:37:01 +08:00

sdram_data_tb.sv

feat: enhance AXI4 and RIBP interfaces with burst support and address generation

2026-08-13 22:37:01 +08:00

soc_irq_topology_tb.sv

feat: add DVP (Digital Video Processor) support and related formal verification

2026-08-13 08:36:38 +08:00

sysctrl_fault_tb.sv

feat: add RTC wake functionality and related integration

2026-08-10 09:32:30 +08:00

tc_pdk_cells_tb.sv

feat: add formal properties for sysctrl and update related files

2026-08-04 12:50:39 +08:00

timer_tb.sv

refactor: refactor RTL paths and update test descriptions

2026-08-13 13:41:52 +08:00

uart_tb.sv

refactor: refactor RTL paths and update test descriptions

2026-08-13 13:41:52 +08:00

ws2812_dma_tb.sv

refactor: refactor parameter naming conventions and update RTL style

2026-08-13 15:08:24 +08:00

ws2812_tb.sv

refactor: refactor parameter naming conventions and update RTL style

2026-08-13 15:08:24 +08:00

xpi_io_tb.sv

feat: implement XPI output-enable isolation test and add related testbench

2026-08-02 19:18:45 +08:00