mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
2840d22e96
- Updated to integrate a coefficient engine and additional signals for coefficient handling. - Modified to include a coefficient engine, enhancing the encoding process with new signals. - Improved to validate generated blocks against expected values and added timeout handling. - Introduced for testing SRAM wrappers in JPEG workspace. - Enhanced test coverage in to reject invalid STA net drivers. - Updated to ensure proper coverage of canonical domains in timing contracts. - Added a new test for JPEG coefficient engine in . - Improved memory map tests in to validate public active MMIO regions. - Enhanced management core specification tests in to verify high-performance core specifications. - Added behavioral-only checks in to exclude synthesis and netlist consumers. - Updated SDRAM tests in to track active firmware memory. - Enhanced STA constraints tests in to cover current clock domains and net drivers.
383 lines
12 KiB
Systemverilog
383 lines
12 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND.
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module jpeg_mcu_reconstructor (
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// verilog_format: off -- preserve command, block, and raster-stream interface columns
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input logic clk_i,
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input logic rst_n_i,
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input logic start_i,
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input logic [ 1:0] sampling_i,
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input logic [ 2:0] format_i,
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input logic [ 4:0] valid_width_i,
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input logic [ 4:0] valid_height_i,
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input logic [511:0] block_i,
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input logic block_valid_i,
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output logic block_ready_o,
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output logic start_ready_o,
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axi4_stream_if.source pixel_axis,
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output logic done_o,
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output logic error_o
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// verilog_format: on
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);
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typedef enum logic [2:0] {
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Idle,
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Load,
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Pixels,
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Nv12Chroma,
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Done
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} state_e;
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state_e s_state_d;
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state_e s_state_q;
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logic [ 2:0] s_state_bits_q;
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logic [ 1:0] s_sampling_d;
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logic [ 1:0] s_sampling_q;
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logic [ 2:0] s_format_d;
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logic [ 2:0] s_format_q;
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logic [ 4:0] s_width_d;
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logic [ 4:0] s_width_q;
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logic [ 4:0] s_height_d;
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logic [ 4:0] s_height_q;
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logic [ 2:0] s_block_cnt_d;
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logic [ 2:0] s_block_cnt_q;
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logic [ 5:0][511:0] s_blocks_q;
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logic [ 4:0] s_x_d;
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logic [ 4:0] s_x_q;
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logic [ 4:0] s_y_d;
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logic [ 4:0] s_y_q;
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logic s_err_d;
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logic s_err_q;
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logic [ 2:0] s_expected_blocks;
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logic [ 7:0] s_y0;
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logic [ 7:0] s_y1;
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logic [ 7:0] s_cb0;
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logic [ 7:0] s_cb1;
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logic [ 7:0] s_cr0;
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logic [ 7:0] s_cr1;
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logic [ 7:0] s_red0;
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logic [ 7:0] s_green0;
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logic [ 7:0] s_blue0;
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logic [ 7:0] s_red1;
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logic [ 7:0] s_green1;
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logic [ 7:0] s_blue1;
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logic [15:0] s_rgb565_0;
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logic [15:0] s_rgb565_1;
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logic s_second_valid;
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logic s_pixel_accept;
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logic [ 4:0] s_x_next;
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logic [ 5:0] s_block_write_en;
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function automatic logic [7:0] block_sample(input logic [511:0] block_i, input logic [2:0] x_i,
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input logic [2:0] y_i);
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return block_i[((y_i*8)+x_i)*8+:8];
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endfunction
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function automatic logic [7:0] clamp_color(input logic signed [17:0] value_i);
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if (value_i < 0) begin
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return 8'd0;
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end
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if (value_i > 255) begin
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return 8'd255;
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end
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return value_i[7:0];
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endfunction
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function automatic logic [23:0] ycbcr_to_rgb(input logic [7:0] y_i, input logic [7:0] cb_i,
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input logic [7:0] cr_i);
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logic signed [ 9:0] s_cb;
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logic signed [ 9:0] s_cr;
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logic signed [17:0] s_red;
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logic signed [17:0] s_green;
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logic signed [17:0] s_blue;
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begin
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s_cb = $signed({1'b0, cb_i}) - 10'sd128;
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s_cr = $signed({1'b0, cr_i}) - 10'sd128;
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s_red = $signed(18'({1'b0, y_i})) + ((18'sd359 * s_cr + 18'sd128) >>> 8);
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s_green = $signed(18'({1'b0, y_i})) - ((18'sd88 * s_cb + 18'sd183 * s_cr + 18'sd128) >>> 8);
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s_blue = $signed(18'({1'b0, y_i})) + ((18'sd454 * s_cb + 18'sd128) >>> 8);
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return {clamp_color(s_red), clamp_color(s_green), clamp_color(s_blue)};
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end
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endfunction
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function automatic logic [7:0] average_chroma(input logic [7:0] left_i,
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input logic [7:0] right_i);
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logic [8:0] s_sum;
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begin
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s_sum = {1'b0, left_i} + {1'b0, right_i} + 1'b1;
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return s_sum[8:1];
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end
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endfunction
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always_comb begin
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unique case (s_sampling_q)
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2'd0: s_expected_blocks = 3'd1;
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2'd1: s_expected_blocks = 3'd3;
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2'd2: s_expected_blocks = 3'd4;
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default: s_expected_blocks = 3'd6;
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endcase
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end
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always_comb begin
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s_y0 = 8'd0;
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s_y1 = 8'd0;
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s_cb0 = 8'd128;
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s_cb1 = 8'd128;
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s_cr0 = 8'd128;
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s_cr1 = 8'd128;
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unique case (s_sampling_q)
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2'd0: begin
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s_y0 = block_sample(s_blocks_q[0], s_x_q[2:0], s_y_q[2:0]);
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s_y1 = block_sample(s_blocks_q[0], s_x_next[2:0], s_y_q[2:0]);
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end
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2'd1: begin
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s_y0 = block_sample(s_blocks_q[0], s_x_q[2:0], s_y_q[2:0]);
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s_y1 = block_sample(s_blocks_q[0], s_x_next[2:0], s_y_q[2:0]);
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s_cb0 = block_sample(s_blocks_q[1], s_x_q[2:0], s_y_q[2:0]);
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s_cb1 = block_sample(s_blocks_q[1], s_x_next[2:0], s_y_q[2:0]);
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s_cr0 = block_sample(s_blocks_q[2], s_x_q[2:0], s_y_q[2:0]);
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s_cr1 = block_sample(s_blocks_q[2], s_x_next[2:0], s_y_q[2:0]);
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end
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2'd2: begin
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s_y0 = block_sample(s_blocks_q[s_x_q[3]], s_x_q[2:0], s_y_q[2:0]);
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s_y1 = block_sample(s_blocks_q[s_x_next[3]], s_x_next[2:0], s_y_q[2:0]);
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s_cb0 = block_sample(s_blocks_q[2], s_x_q[3:1], s_y_q[2:0]);
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s_cb1 = block_sample(s_blocks_q[2], s_x_next[3:1], s_y_q[2:0]);
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s_cr0 = block_sample(s_blocks_q[3], s_x_q[3:1], s_y_q[2:0]);
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s_cr1 = block_sample(s_blocks_q[3], s_x_next[3:1], s_y_q[2:0]);
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end
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default: begin
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s_y0 = block_sample(s_blocks_q[{s_y_q[3], s_x_q[3]}], s_x_q[2:0], s_y_q[2:0]);
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s_y1 = block_sample(s_blocks_q[{s_y_q[3], s_x_next[3]}], s_x_next[2:0], s_y_q[2:0]);
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s_cb0 = block_sample(s_blocks_q[4], s_x_q[3:1], s_y_q[3:1]);
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s_cb1 = block_sample(s_blocks_q[4], s_x_next[3:1], s_y_q[3:1]);
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s_cr0 = block_sample(s_blocks_q[5], s_x_q[3:1], s_y_q[3:1]);
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s_cr1 = block_sample(s_blocks_q[5], s_x_next[3:1], s_y_q[3:1]);
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end
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endcase
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end
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assign {s_red0, s_green0, s_blue0} = ycbcr_to_rgb(s_y0, s_cb0, s_cr0);
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assign {s_red1, s_green1, s_blue1} = ycbcr_to_rgb(s_y1, s_cb1, s_cr1);
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assign s_rgb565_0 = {s_red0[7:3], s_green0[7:2], s_blue0[7:3]};
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assign s_rgb565_1 = {s_red1[7:3], s_green1[7:2], s_blue1[7:3]};
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assign s_x_next = s_x_q + 1'b1;
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assign s_second_valid = (s_x_q + 1'b1) < s_width_q;
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assign s_pixel_accept = pixel_axis.tvalid && pixel_axis.tready;
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assign s_state_q = state_e'(s_state_bits_q);
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assign start_ready_o = s_state_q == Idle;
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assign block_ready_o = s_state_q == Load;
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assign done_o = s_state_q == Done;
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assign error_o = s_err_q;
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assign s_block_write_en = ((s_state_q == Load) && block_valid_i) ?
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(6'b000001 << s_block_cnt_q) : 6'b000000;
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// Every required block is loaded before Pixels, so the block bank needs no reset.
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for (genvar block_index = 0; block_index < 6; block_index++) begin : gen_block_register
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dffl #(
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.DATA_WIDTH(512)
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) u_block_dffl (
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.clk_i(clk_i),
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.en_i (s_block_write_en[block_index]),
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.dat_i(block_i),
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.dat_o(s_blocks_q[block_index])
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);
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end
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always_comb begin
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pixel_axis.tdata = '0;
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pixel_axis.tkeep = '0;
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pixel_axis.tstrb = '0;
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pixel_axis.tlast = 1'b0;
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pixel_axis.tid = '0;
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pixel_axis.tdest = '0;
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pixel_axis.tuser = '0;
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pixel_axis.tvalid = (s_state_q == Pixels) || (s_state_q == Nv12Chroma);
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if (s_state_q == Nv12Chroma) begin
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pixel_axis.tdata[7:0] = s_cb0;
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pixel_axis.tdata[15:8] = s_cr0;
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pixel_axis.tkeep = 8'h03;
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pixel_axis.tstrb = 8'h03;
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pixel_axis.tlast = (s_x_q + 2 >= s_width_q);
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pixel_axis.tdest = 1'b1;
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pixel_axis.tuser = (s_x_q == 5'd0) && (s_y_q == 5'd0);
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end else begin
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unique case (s_format_q)
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3'd0: begin
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pixel_axis.tdata[7:0] = s_y0;
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pixel_axis.tdata[15:8] = s_y1;
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pixel_axis.tkeep = s_second_valid ? 8'h03 : 8'h01;
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end
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3'd1: begin
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pixel_axis.tdata[15:0] = s_rgb565_0;
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pixel_axis.tdata[31:16] = s_rgb565_1;
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pixel_axis.tkeep = s_second_valid ? 8'h0f : 8'h03;
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end
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3'd2: begin
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pixel_axis.tdata[23:0] = {s_blue0, s_green0, s_red0};
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pixel_axis.tdata[47:24] = {s_blue1, s_green1, s_red1};
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pixel_axis.tkeep = s_second_valid ? 8'h3f : 8'h07;
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end
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3'd3: begin
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pixel_axis.tdata[31:0] = {
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average_chroma(s_cr0, s_cr1), s_y1, average_chroma(s_cb0, s_cb1), s_y0
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};
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pixel_axis.tkeep = 8'h0f;
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end
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default: begin
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pixel_axis.tdata[7:0] = s_y0;
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pixel_axis.tdata[15:8] = s_y1;
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pixel_axis.tkeep = s_second_valid ? 8'h03 : 8'h01;
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end
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endcase
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pixel_axis.tstrb = pixel_axis.tkeep;
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pixel_axis.tlast = (s_x_q + 2 >= s_width_q);
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pixel_axis.tuser = (s_x_q == 5'd0) && (s_y_q == 5'd0);
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end
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end
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always_comb begin
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s_state_d = s_state_q;
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s_sampling_d = s_sampling_q;
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s_format_d = s_format_q;
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s_width_d = s_width_q;
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s_height_d = s_height_q;
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s_block_cnt_d = s_block_cnt_q;
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s_x_d = s_x_q;
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s_y_d = s_y_q;
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s_err_d = s_err_q;
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unique case (s_state_q)
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Idle: begin
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if (start_i) begin
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s_sampling_d = sampling_i;
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s_format_d = format_i;
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s_width_d = valid_width_i;
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s_height_d = valid_height_i;
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s_block_cnt_d = 3'd0;
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s_x_d = 5'd0;
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s_y_d = 5'd0;
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s_err_d = (format_i > 3'd4) || (valid_width_i == 5'd0) ||
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(valid_height_i == 5'd0) || (valid_width_i > 5'd16) ||
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(valid_height_i > 5'd16);
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s_state_d = Load;
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end
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end
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Load: begin
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if (block_valid_i) begin
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if (s_block_cnt_q + 1'b1 == s_expected_blocks) begin
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s_x_d = 5'd0;
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s_y_d = 5'd0;
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s_state_d = Pixels;
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end else begin
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s_block_cnt_d = s_block_cnt_q + 1'b1;
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end
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end
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end
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Pixels: begin
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if (s_pixel_accept) begin
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if (s_x_q + 2 >= s_width_q) begin
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s_x_d = 5'd0;
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if (s_y_q + 1'b1 >= s_height_q) begin
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s_y_d = 5'd0;
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s_state_d = (s_format_q == 3'd4 && s_sampling_q != 2'd0) ? Nv12Chroma : Done;
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end else begin
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s_y_d = s_y_q + 1'b1;
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end
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end else begin
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s_x_d = s_x_q + 2;
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end
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end
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end
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Nv12Chroma: begin
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if (s_pixel_accept) begin
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if (s_x_q + 2 >= s_width_q) begin
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s_x_d = 5'd0;
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if (s_y_q + 2 >= s_height_q) begin
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s_state_d = Done;
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end else begin
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s_y_d = s_y_q + 2;
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end
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end else begin
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s_x_d = s_x_q + 2;
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end
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end
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end
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Done: begin
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s_state_d = Idle;
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end
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default: s_state_d = Idle;
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endcase
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end
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dffr #(
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.DATA_WIDTH(3)
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) u_state_dffr (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_state_d),
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.dat_o (s_state_bits_q)
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);
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dffr #(
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.DATA_WIDTH(2)
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) u_sampling_dffr (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_sampling_d),
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.dat_o (s_sampling_q)
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);
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dffr #(
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.DATA_WIDTH(3)
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) u_format_dffr (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_format_d),
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.dat_o (s_format_q)
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);
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dffr #(
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.DATA_WIDTH(5)
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) u_width_dffr (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_width_d),
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.dat_o (s_width_q)
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);
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dffr #(
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.DATA_WIDTH(5)
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) u_height_dffr (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_height_d),
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.dat_o (s_height_q)
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);
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dffr #(
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.DATA_WIDTH(3)
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) u_block_cnt_dffr (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_block_cnt_d),
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.dat_o (s_block_cnt_q)
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);
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dffr #(
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.DATA_WIDTH(5)
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) u_x_dffr (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_x_d),
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.dat_o (s_x_q)
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);
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dffr #(
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.DATA_WIDTH(5)
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) u_y_dffr (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_y_d),
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.dat_o (s_y_q)
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);
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dffr u_err_dffr (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_err_d),
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.dat_o (s_err_q)
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);
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endmodule
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