mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
2840d22e96
- Updated to integrate a coefficient engine and additional signals for coefficient handling. - Modified to include a coefficient engine, enhancing the encoding process with new signals. - Improved to validate generated blocks against expected values and added timeout handling. - Introduced for testing SRAM wrappers in JPEG workspace. - Enhanced test coverage in to reject invalid STA net drivers. - Updated to ensure proper coverage of canonical domains in timing contracts. - Added a new test for JPEG coefficient engine in . - Improved memory map tests in to validate public active MMIO regions. - Enhanced management core specification tests in to verify high-performance core specifications. - Added behavioral-only checks in to exclude synthesis and netlist consumers. - Updated SDRAM tests in to track active firmware memory. - Enhanced STA constraints tests in to cover current clock domains and net drivers.
186 lines
16 KiB
JSON
186 lines
16 KiB
JSON
{
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"schema_version": 2,
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"reset_ports": ["ext_rst_n_i_pad", "jtag_trst_n_i_pad"],
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"domains": [
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{
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"name": "aon",
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"clock": "s_ref24_clk_buf",
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"reset": "s_aon_rst_n",
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"reset_source": "ext_rst_n_i",
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"reset_primitive": "rst_sync",
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"path": "rtl/mini/top/soc_clock_reset_subsystem.sv",
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"instance": "u_aon_rst_sync",
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"sta": {"source_port": "ref24clk_i_pad", "pin": "u_rcu.u_clock_reset_subsystem.u_ref24_clk_buf/clk_o", "period_ns": 41.666666667, "async_group": "aon"}
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},
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{
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"name": "lp",
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"clock": "s_lp_root_clk",
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"reset": "lp_rst_n_o",
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"reset_source": "s_domain_reset_source_n",
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"reset_primitive": "rst_sync",
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"path": "rtl/mini/top/soc_clock_reset_subsystem.sv",
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"instance": "u_lp_rst_sync",
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"sta": {"source_domain": "aon", "object_type": "net_driver", "net": "s_sys_clk", "period_ns": 13.888888889, "async_group": "lp"}
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},
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{
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"name": "hp",
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"clock": "s_hp_root_clk",
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"reset": "hp_rst_n_o",
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"reset_source": "s_domain_reset_source_n",
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"reset_primitive": "rst_sync",
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"path": "rtl/mini/top/soc_clock_reset_subsystem.sv",
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"instance": "u_hp_rst_sync",
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"sta": {"source_port": "extclk_i_pad", "object_type": "net_driver", "net": "s_hp_clk", "period_ns": 4.166666667, "async_group": "hp"}
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},
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{
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"name": "pclk",
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"clock": "s_pclk",
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"reset": "pclk_rst_n_o",
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"reset_source": "s_domain_reset_source_n",
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"reset_primitive": "rst_sync",
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"path": "rtl/mini/top/soc_clock_reset_subsystem.sv",
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"instance": "u_pclk_rst_sync",
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"sta": {"source_domain": "lp", "object_type": "net_driver", "net": "s_pclk", "period_ns": 20.833333333, "async_group": "lp"}
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},
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{
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"name": "memory",
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"clock": "s_mem_clk_div2",
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"reset": "mem_rst_n_o",
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"reset_source": "s_domain_reset_source_n",
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"reset_primitive": "rst_sync",
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"path": "rtl/mini/top/soc_clock_reset_subsystem.sv",
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"instance": "u_mem_rst_sync",
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"sta": {"source_port": "extclk_i_pad", "object_type": "net_driver", "net": "s_mem_clk", "period_ns": 27.777777778, "async_group": "memory"}
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},
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{
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"name": "audio",
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"clock": "s_aud_clk_buf",
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"reset": "aud_rst_n_o",
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"reset_source": "s_domain_reset_source_n",
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"reset_primitive": "rst_sync",
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"path": "rtl/mini/top/soc_clock_reset_subsystem.sv",
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"instance": "u_aud_rst_sync",
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"sta": {"source_port": "audclk_i_pad", "pin": "u_rcu.u_clock_reset_subsystem.u_aud_clk_buf/clk_o", "period_ns": 54.253472222, "async_group": "audio"}
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},
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{
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"name": "jtag",
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"clock": "s_jtag_tck_buf",
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"reset": "s_jtag_trst_n_sync",
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"reset_source": "jtag_trst_n_i",
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"reset_primitive": "rst_sync",
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"path": "rtl/mini/top/mgmt_debug_wrapper.sv",
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"instance": "u_jtag_rst_sync",
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"sta": {"source_port": "jtag_tck_i_pad", "object_type": "port", "period_ns": 100.0, "async_group": "jtag"}
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},
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{
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"name": "dvp",
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"clock": "s_pclk_sel",
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"reset": "s_dvp_pclk_rst_n_sync",
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"reset_source": "rst_n_i",
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"reset_primitive": "rst_sync",
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"path": "rtl/ip/multimedia/axi4s_dvp.sv",
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"instance": "u_dvp_pclk_rst_sync",
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"sta": {"source_port": "gpio_10_io_pad", "pin": "u_retrosoc.u_apb4_periph.u_axi4_dvp.u_dvp_pclk_clk_buf/clk_o", "period_ns": 41.666666667, "async_group": "dvp"}
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},
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{
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"name": "usb2_ulpi",
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"clock": "clk_ulpi_i",
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"reset": "s_ulpi_rst_n",
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"reset_source": "rst_n_i",
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"reset_primitive": "rst_sync",
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"path": "rtl/ip/usb/apb4_usb2.sv",
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"instance": "u_ulpi_rst_sync",
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"sta": {"source_port": "usb2_ulpi_clk_i_pad", "object_type": "port", "period_ns": 16.666666667, "async_group": "usb2_ulpi"}
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}
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],
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"crossings": [
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{"name": "pll_request", "source": "pclk", "destination": "aon", "primitive": "cdc_2phase", "path": "rtl/mini/top/pll_rcu_controller.sv", "instance": "u_pll_req_cdc"},
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{"name": "pll_response", "source": "aon", "destination": "pclk", "primitive": "cdc_2phase", "path": "rtl/mini/top/pll_rcu_controller.sv", "instance": "u_pll_rsp_cdc"},
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{"name": "clock_request", "source": "pclk", "destination": "aon", "primitive": "cdc_2phase", "path": "rtl/mini/top/clock_config_controller.sv", "instance": "u_clock_req_cdc"},
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{"name": "clock_response", "source": "aon", "destination": "pclk", "primitive": "cdc_2phase", "path": "rtl/mini/top/clock_config_controller.sv", "instance": "u_clock_rsp_cdc"},
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{"name": "pclk_config", "source": "aon", "destination": "lp", "primitive": "cdc_2phase", "path": "rtl/mini/top/soc_clock_reset_subsystem.sv", "instance": "u_pclk_cfg_cdc"},
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{"name": "hp_idle", "source": "hp", "destination": "aon", "primitive": "cdc_sync", "path": "rtl/mini/top/soc_clock_reset_subsystem.sv", "instance": "u_hp_idle_sync"},
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{"name": "pclk_idle", "source": "pclk", "destination": "aon", "primitive": "cdc_sync", "path": "rtl/mini/top/soc_clock_reset_subsystem.sv", "instance": "u_pclk_idle_sync"},
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{"name": "clint_timebase", "source": "aon", "destination": "lp", "primitive": "edge_det", "path": "rtl/ip/peripheral/clint_timebase.sv", "instance": "u_tick_edge_det"},
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{"name": "hp_mmio", "source": "hp", "destination": "lp", "primitive": "axi4_async_bridge", "path": "rtl/mini/top/retrosoc.sv", "instance": "u_hp_mmio_cdc"},
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{"name": "cfg_registers", "source": "lp", "destination": "pclk", "primitive": "axi4_async_bridge", "path": "rtl/mini/top/retrosoc.sv", "instance": "u_cfg_pclk_cdc"},
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{"name": "system_registers", "source": "lp", "destination": "pclk", "primitive": "axi4_async_bridge", "path": "rtl/mini/top/retrosoc.sv", "instance": "u_system_pclk_cdc"},
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{"name": "sdram_config", "source": "pclk", "destination": "memory", "primitive": "apb4_async_bridge", "path": "rtl/mini/top/retrosoc.sv", "instance": "u_sdram_cfg_cdc"},
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{"name": "sram_config", "source": "pclk", "destination": "hp", "primitive": "apb4_async_bridge", "path": "rtl/mini/top/retrosoc.sv", "instance": "u_sram_cfg_cdc"},
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{"name": "fabric_monitor", "source": "pclk", "destination": "hp", "primitive": "apb4_async_bridge", "path": "rtl/mini/top/retrosoc.sv", "instance": "u_fabric_monitor_cdc"},
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{"name": "io_dma_data", "source": "pclk", "destination": "hp", "primitive": "axi4_async_bridge", "path": "rtl/mini/top/soc_data_plane.sv", "instance": "u_io_cdc"},
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{"name": "jpeg_data", "source": "pclk", "destination": "hp", "primitive": "axi4_async_bridge", "path": "rtl/mini/top/soc_data_plane.sv", "instance": "u_jpeg_cdc"},
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{"name": "extension_h_data", "source": "pclk", "destination": "hp", "primitive": "axi4_async_bridge", "path": "rtl/mini/top/soc_data_plane.sv", "instance": "u_ext_h_cdc"},
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{"name": "sdram_data", "source": "hp", "destination": "memory", "primitive": "axi4_async_bridge", "path": "rtl/mini/top/soc_data_plane.sv", "instance": "u_target_cdc"},
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{"name": "serial_memory_data", "source": "hp", "destination": "memory", "primitive": "axi4_async_bridge", "path": "rtl/mini/top/soc_data_plane.sv", "instance": "u_target_cdc"},
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{"name": "sdram_abort", "source": "hp", "destination": "memory", "primitive": "cdc_sync", "path": "rtl/mini/top/soc_data_plane.sv", "instance": "u_abort_sync"},
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{"name": "hp_cache_request", "source": "aon", "destination": "pclk", "primitive": "cdc_sync", "path": "rtl/mini/top/retrosoc.sv", "instance": "u_hp_cache_req_sync"},
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{"name": "hp_cache_clean", "source": "pclk", "destination": "aon", "primitive": "cdc_sync", "path": "rtl/mini/top/retrosoc.sv", "instance": "u_hp_cache_clean_sync"},
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{"name": "resource_block", "source": "pclk", "destination": "hp", "primitive": "cdc_sync", "path": "rtl/mini/top/soc_data_plane.sv", "instance": "u_resource_block_sync"},
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{"name": "resource_idle", "source": "hp", "destination": "pclk", "primitive": "cdc_sync", "path": "rtl/mini/top/retrosoc.sv", "instance": "u_resource_idle_sync"},
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{"name": "resource_block_ack", "source": "hp", "destination": "pclk", "primitive": "cdc_sync", "path": "rtl/mini/top/retrosoc.sv", "instance": "u_resource_block_ack_sync"},
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{"name": "memory_pad_mode_hp", "source": "aon", "destination": "hp", "primitive": "cdc_sync", "path": "rtl/mini/top/soc_data_plane.sv", "instance": "u_mem_pad_mode_sync"},
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{"name": "memory_pad_mode_lp", "source": "aon", "destination": "lp", "primitive": "cdc_sync", "path": "rtl/mini/top/retrosoc.sv", "instance": "u_mem_pad_mode_sync"},
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{"name": "dvp_enable", "source": "pclk", "destination": "dvp", "primitive": "cdc_2phase", "path": "rtl/ip/multimedia/axi4s_dvp.sv", "instance": "u_dvp_config_cdc"},
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{"name": "dvp_fifo", "source": "dvp", "destination": "pclk", "primitive": "cdc_fifo_warm_flush", "path": "rtl/ip/multimedia/axi4s_dvp.sv", "instance": "u_dvp_payload_fifo"},
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{"name": "rtc_command", "source": "pclk", "destination": "audio", "primitive": "async_reqack", "path": "rtl/managed/clusterip/rtc/rtl/apb4_rtc.sv", "instance": "u_command_mailbox"},
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{"name": "rtc_response", "source": "audio", "destination": "pclk", "primitive": "async_reqack", "path": "rtl/managed/clusterip/rtc/rtl/apb4_rtc.sv", "instance": "u_response_mailbox"},
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{"name": "rtc_event", "source": "audio", "destination": "pclk", "primitive": "cdc_sync", "path": "rtl/managed/clusterip/rtc/rtl/apb4_rtc.sv", "instance": "u_event_sync"},
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{"name": "rtc_status", "source": "audio", "destination": "pclk", "primitive": "cdc_sync", "path": "rtl/managed/clusterip/rtc/rtl/apb4_rtc.sv", "instance": "u_status_sync"},
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{"name": "rtc_interrupt_enable", "source": "audio", "destination": "pclk", "primitive": "cdc_sync", "path": "rtl/managed/clusterip/rtc/rtl/apb4_rtc.sv", "instance": "u_interrupt_enable_sync"},
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{"name": "rtc_wake_enable", "source": "audio", "destination": "pclk", "primitive": "cdc_sync", "path": "rtl/managed/clusterip/rtc/rtl/apb4_rtc.sv", "instance": "u_wake_enable_sync"},
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{"name": "rtc_wake_status", "source": "audio", "destination": "pclk", "primitive": "cdc_sync", "path": "rtl/ip/peripheral/sysctrl_core.sv", "instance": "u_rtc_wake_sync"},
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{"name": "jtag_dmi", "source": "jtag", "destination": "lp", "primitive": "hazard3_apb_async_bridge", "path": "rtl/managed/hazard3/hdl/debug/dtm/hazard3_jtag_dtm_core.v", "instance": "inst_hazard3_apb_async_bridge"},
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{"name": "hp_debug_select", "source": "pclk", "destination": "jtag", "primitive": "cdc_sync", "path": "rtl/mini/top/retrosoc.sv", "instance": "u_debug_select_sync"},
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{"name": "wdg_command", "source": "pclk", "destination": "audio", "primitive": "async_reqack", "path": "rtl/managed/clusterip/wdg/rtl/apb4_wdg.sv", "instance": "u_command_mailbox"},
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{"name": "wdg_response", "source": "audio", "destination": "pclk", "primitive": "async_reqack", "path": "rtl/managed/clusterip/wdg/rtl/apb4_wdg.sv", "instance": "u_response_mailbox"},
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{"name": "wdg_debug_halted", "source": "lp", "destination": "audio", "primitive": "cdc_sync", "path": "rtl/managed/clusterip/wdg/rtl/apb4_wdg.sv", "instance": "u_debug_halted_sync"},
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{"name": "wdg_status", "source": "audio", "destination": "pclk", "primitive": "cdc_sync", "path": "rtl/managed/clusterip/wdg/rtl/apb4_wdg.sv", "instance": "u_status_sync"},
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{"name": "wdg_reset_cause", "source": "audio", "destination": "pclk", "primitive": "cdc_sync", "path": "rtl/managed/clusterip/wdg/rtl/apb4_wdg.sv", "instance": "u_reset_cause_sync"},
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{"name": "usb2_work", "source": "pclk", "destination": "usb2_ulpi", "primitive": "async_reqack", "path": "rtl/ip/usb/apb4_usb2.sv", "instance": "u_work_cdc"},
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{"name": "usb2_result", "source": "usb2_ulpi", "destination": "pclk", "primitive": "async_reqack", "path": "rtl/ip/usb/apb4_usb2.sv", "instance": "u_result_cdc"},
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{"name": "usb2_setup", "source": "usb2_ulpi", "destination": "pclk", "primitive": "async_reqack", "path": "rtl/ip/usb/apb4_usb2.sv", "instance": "u_setup_cdc"},
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{"name": "usb2_fill_command", "source": "pclk", "destination": "usb2_ulpi", "primitive": "async_reqack", "path": "rtl/ip/usb/apb4_usb2.sv", "instance": "u_fill_command_cdc"},
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{"name": "usb2_drain_command", "source": "pclk", "destination": "usb2_ulpi", "primitive": "async_reqack", "path": "rtl/ip/usb/apb4_usb2.sv", "instance": "u_drain_command_cdc"},
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{"name": "usb2_buffer_event", "source": "usb2_ulpi", "destination": "pclk", "primitive": "async_reqack", "path": "rtl/ip/usb/apb4_usb2.sv", "instance": "u_buffer_event_cdc"},
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{"name": "usb2_view_request", "source": "pclk", "destination": "usb2_ulpi", "primitive": "async_reqack", "path": "rtl/ip/usb/apb4_usb2.sv", "instance": "u_view_request_cdc"},
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{"name": "usb2_view_response", "source": "usb2_ulpi", "destination": "pclk", "primitive": "async_reqack", "path": "rtl/ip/usb/apb4_usb2.sv", "instance": "u_view_response_cdc"},
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{"name": "usb2_fill_stream", "source": "pclk", "destination": "usb2_ulpi", "primitive": "cdc_fifo", "path": "rtl/ip/usb/apb4_usb2.sv", "instance": "u_fill_stream_cdc"},
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{"name": "usb2_drain_stream", "source": "usb2_ulpi", "destination": "pclk", "primitive": "cdc_fifo", "path": "rtl/ip/usb/apb4_usb2.sv", "instance": "u_drain_stream_cdc"},
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{"name": "usb2_role", "source": "pclk", "destination": "usb2_ulpi", "primitive": "cdc_sync", "path": "rtl/ip/usb/apb4_usb2.sv", "instance": "u_role_sync"},
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{"name": "usb2_role_reset", "source": "pclk", "destination": "usb2_ulpi", "primitive": "cdc_sync", "path": "rtl/ip/usb/apb4_usb2.sv", "instance": "u_role_reset_sync"},
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{"name": "usb2_phy_reset", "source": "pclk", "destination": "usb2_ulpi", "primitive": "cdc_sync", "path": "rtl/ip/usb/apb4_usb2.sv", "instance": "u_phy_reset_sync"},
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{"name": "usb2_high_speed", "source": "pclk", "destination": "usb2_ulpi", "primitive": "cdc_sync", "path": "rtl/ip/usb/apb4_usb2.sv", "instance": "u_high_speed_sync"},
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{"name": "usb2_enable", "source": "pclk", "destination": "usb2_ulpi", "primitive": "cdc_sync", "path": "rtl/ip/usb/apb4_usb2.sv", "instance": "u_enable_sync"},
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{"name": "usb2_device_addr", "source": "pclk", "destination": "usb2_ulpi", "primitive": "cdc_sync", "path": "rtl/ip/usb/apb4_usb2.sv", "instance": "u_device_addr_sync"},
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{"name": "usb2_endpoint_config", "source": "pclk", "destination": "usb2_ulpi", "primitive": "cdc_sync", "path": "rtl/ip/usb/apb4_usb2.sv", "instance": "u_endpoint_cfg_sync"},
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{"name": "usb2_timeout", "source": "pclk", "destination": "usb2_ulpi", "primitive": "cdc_sync", "path": "rtl/ip/usb/apb4_usb2.sv", "instance": "u_timeout_sync"},
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{"name": "usb2_phy_status", "source": "usb2_ulpi", "destination": "pclk", "primitive": "cdc_sync", "path": "rtl/ip/usb/apb4_usb2.sv", "instance": "u_phy_status_sync"},
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{"name": "usb2_transaction_busy", "source": "usb2_ulpi", "destination": "pclk", "primitive": "cdc_sync", "path": "rtl/ip/usb/apb4_usb2.sv", "instance": "u_transaction_busy_sync"},
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{"name": "usb2_frame", "source": "usb2_ulpi", "destination": "pclk", "primitive": "cdc_sync", "path": "rtl/ip/usb/apb4_usb2.sv", "instance": "u_frame_sync"},
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{"name": "usb2_ecc_counts", "source": "usb2_ulpi", "destination": "pclk", "primitive": "cdc_sync", "path": "rtl/ip/usb/apb4_usb2.sv", "instance": "u_ecc_counts_sync"},
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{"name": "usb2_retry_event", "source": "usb2_ulpi", "destination": "pclk", "primitive": "edge_det", "path": "rtl/ip/usb/apb4_usb2.sv", "instance": "u_retry_event_sync"},
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{"name": "usb2_protocol_event", "source": "usb2_ulpi", "destination": "pclk", "primitive": "edge_det", "path": "rtl/ip/usb/apb4_usb2.sv", "instance": "u_protocol_event_sync"}
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],
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"same_domain_contracts": [
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{
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"name": "lp_pclk_generated_clock",
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"source_domain": "lp",
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"destination_domain": "pclk",
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"clock": "clk_pclk_i",
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"reset": "rst_pclk_n_i",
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"relationship": "synchronous_generated_clock",
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"description": "PCLK is generated from LP by /1, /2, /4, /8, or /16; STA must not false-path it."
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},
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{
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"name": "memory_protocol_transition",
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"source_domain": "hp",
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"destination_domain": "memory",
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"clock": "clk_mem_i",
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"reset": "rst_mem_n_i",
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"relationship": "declared_transition_boundary",
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"description": "SDRAM AXI64 commands cross from HP into the stable 36 MHz memory domain; refresh and protocol timing do not follow HP DFS."
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}
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]
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}
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