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maksyuki
921f8caa64
- Updated to validate C, Makefile, and RTL formatting in addition to existing checks for Python, YAML, and GitHub Actions. - Added new dependencies to for improved formatting and documentation tools. - Introduced a new script to format or verify tracked self-owned Makefile and RTL sources. - Improved RTL code formatting across multiple files by ensuring consistent spacing and line endings. - Refactored various RTL modules to enhance readability and maintainability. - Added unit tests for the new formatting functionality to ensure correct behavior.
Static Timing Analysis
This directory contains OpenSTA constraints, Tcl setup, and Make integration for retroSoC timing analysis. The selected profile and synthesized netlist define the actual timing context.
Run synthesis before timing analysis, then invoke the supported OpenSTA flow:
make CONFIG=configs/ci/hazard3-rv32im-ihp130.mk SYNTH=YOSYS synth
make CONFIG=configs/ci/hazard3-rv32im-ihp130.mk STA=OPENSTA sta
Review WNS/TNS and warning changes through the generated reports and quality checks. Timing results are PDK/tool/profile dependent; do not compare unrelated variants as a gate.