mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
2b6819449c
- Added interface to and implemented error handling for register writes. - Introduced a new test for AXI4 address gate functionality in . - Updated clock and reset domain assertions in to reflect new domain names. - Modified expected outputs in to include new clock domains. - Adjusted chip configuration assertions in to account for additional power pads. - Enhanced memory map tests in with new definitions and includes. - Updated pin mapping tests in to include new reference clock pads. - Improved script tools tests in to ensure correct validation of extension bindings. - Refined system control tests in to include new clock control interface. - Updated USB2 packet RAM tests in to include new SRAM definitions. - Enhanced user extensions tests in to validate new product extension configurations. - Adjusted user IP register parity tests to use legacy extensions. - Updated Yosys synthesis recipe tests to reflect changes in STA period calculations.
15 lines
521 B
Makefile
15 lines
521 B
Makefile
# Copy this file to configs/local/ics55.mk. The local copy and every absolute
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# macro-model path remain ignored by Git.
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include configs/cluster/ics55.mk
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HAVE_PLL := YES
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HAVE_SRAM_IF := YES
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HAVE_SRAM_MACRO := YES
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SRAM_SIZE_KIB := 32
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AUD_CLK_HZ := 18432000
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# Populate both paths from the local ICS_LIB declared by
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# physical/commercial/local/ics55-production.mk. Keep the copied profile and
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# any local PLL_TOP simulation adapter ignored by Git.
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LOCAL_RTL_FILES := REQUIRED_SRAM_MODEL REQUIRED_PLL_MODEL
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