mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
2b6819449c
- Added interface to and implemented error handling for register writes. - Introduced a new test for AXI4 address gate functionality in . - Updated clock and reset domain assertions in to reflect new domain names. - Modified expected outputs in to include new clock domains. - Adjusted chip configuration assertions in to account for additional power pads. - Enhanced memory map tests in with new definitions and includes. - Updated pin mapping tests in to include new reference clock pads. - Improved script tools tests in to ensure correct validation of extension bindings. - Refined system control tests in to include new clock control interface. - Updated USB2 packet RAM tests in to include new SRAM definitions. - Enhanced user extensions tests in to validate new product extension configurations. - Adjusted user IP register parity tests to use legacy extensions. - Updated Yosys synthesis recipe tests to reflect changes in STA period calculations.
96 lines
3.0 KiB
Python
96 lines
3.0 KiB
Python
"""SystemCtrl RTL regression tests."""
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from __future__ import annotations
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import shutil
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import subprocess
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import sys
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from pathlib import Path
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ROOT = Path(__file__).resolve().parents[1]
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PERIPHERAL = ROOT / "rtl/ip/peripheral"
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def test_sysctrl_registers_lifecycle_faults_and_wake(tmp_path: Path) -> None:
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iverilog = shutil.which("iverilog")
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vvp = shutil.which("vvp")
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if iverilog is None or vvp is None:
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return
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common = ROOT / "rtl/managed/clusterip/common/rtl"
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generated = tmp_path / "generated"
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subprocess.run(
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[
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sys.executable,
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str(ROOT / "rtl/mini/address_map/generate_memory_map.py"),
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"--map",
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str(ROOT / "rtl/mini/address_map/memory_map.json"),
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"--output-dir",
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str(generated),
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],
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check=True,
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)
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subprocess.run(
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[
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sys.executable,
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str(ROOT / "rtl/mini/integration/generate_user_extensions.py"),
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"--map",
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str(ROOT / "rtl/mini/integration/user_extensions.json"),
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"--output-dir",
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str(generated / "user_extensions"),
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],
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check=True,
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)
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source_list = tmp_path / "sysctrl.fl"
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source_list.write_text(
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"\n".join(
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[
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"+define+SV_ASSRT_DISABLE",
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"+define+MINI_PRODUCT",
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f"+incdir+{generated / 'rtl'}",
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f"+incdir+{generated / 'user_extensions' / 'rtl'}",
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f"+incdir+{ROOT / 'rtl/mini/top'}",
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f"+incdir+{common}",
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f"+incdir+{common / 'interface'}",
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f"+incdir+{common / 'utils'}",
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f"+incdir+{common / 'cdc'}",
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f"+incdir+{PERIPHERAL}",
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str(common / "interface/apb4_if.sv"),
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str(common / "utils/register.sv"),
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str(common / "cdc/cdc_sync.sv"),
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str(PERIPHERAL / "pll_ctrl_if.sv"),
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str(PERIPHERAL / "clock_ctrl_if.sv"),
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str(PERIPHERAL / "sysctrl_if.sv"),
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str(PERIPHERAL / "sysctrl_define.svh"),
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str(PERIPHERAL / "sysctrl_reg.sv"),
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str(PERIPHERAL / "sysctrl_core.sv"),
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str(PERIPHERAL / "apb4_sysctrl.sv"),
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str(ROOT / "tests/rtl/sysctrl_tb.sv"),
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"",
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]
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),
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encoding="utf-8",
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)
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converted = tmp_path / "sysctrl_tb.v"
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subprocess.run(
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[
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sys.executable,
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str(ROOT / "rtl/mini/script/convt_sv2v.py"),
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"-f",
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str(source_list),
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"--output",
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str(converted),
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],
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check=True,
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)
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simulation = tmp_path / "sysctrl_tb"
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subprocess.run(
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[iverilog, "-g2012", "-s", "sysctrl_tb", "-o", str(simulation), str(converted)],
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check=True,
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)
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result = subprocess.run([vvp, str(simulation)], text=True, capture_output=True, check=True)
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assert "SystemCtrl register, lifecycle, fault, performance, RTC wake, and HP test passed" in (
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result.stdout
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)
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