mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
66 lines
2.8 KiB
Python
66 lines
2.8 KiB
Python
"""Keep the boot display aligned with the fixed Hazard3 management-core integration."""
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from pathlib import Path
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ROOT = Path(__file__).resolve().parents[1]
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BOOTER = ROOT / "crt/src/service/booter.c"
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SOFTWARE_MAKE = ROOT / "rtl/mini/mk/software.mk"
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MGMT_CORE = ROOT / "rtl/mini/top/mgmt_core_wrapper.sv"
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MGMT_DEBUG = ROOT / "rtl/mini/top/mgmt_debug_wrapper.sv"
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AHBL_TO_AXI4 = ROOT / "rtl/mini/top/ahbl2axi4.sv"
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def test_booter_prints_the_fixed_hazard3_specification() -> None:
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booter = BOOTER.read_text(encoding="utf-8")
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software_make = SOFTWARE_MAKE.read_text(encoding="utf-8")
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management_core = MGMT_CORE.read_text(encoding="utf-8")
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management_debug = MGMT_DEBUG.read_text(encoding="utf-8")
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ahbl_to_axi4 = AHBL_TO_AXI4.read_text(encoding="utf-8")
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assert "DEF_VAL += -DRS_SOC_MGMT_JTAG_IDCODE=0x$(JTAG_IDCODE)U" in software_make
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assert "Management-Core Specification:" in booter
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assert "Management Processor:" not in booter
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assert "User Processors:" in booter
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assert "Core: Hazard3(single hart), 3-stage pipeline" in booter
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assert "Base: RV32IMAC_Zicsr" in booter
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assert "Bit manipulation: Zba_Zbb_Zbc_Zbkb_Zbkx_Zbs" in booter
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assert "Other: Zifencei_Zilsd_Xh3BextM_Xh3IRQ" in booter
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assert "Not present: U-mode PMP Zcb_Zclsd_Zcmp_Xh3PMPM_Xh3Power" in booter
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assert "IRQ: 30 external + software + timer; Xh3IRQ, 4 priority levels" in booter
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assert "one shared instruction/data AHB5 manager port" in booter
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assert "single-beat AXI4 normal access" in booter
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assert "no burst, lock, or global-exclusive forwarding; no system A atomics" in booter
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assert "RS_SOC_MGMT_JTAG_IDCODE" in booter
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assert "halted-hart memory commands; system bus access disabled" in booter
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assert "2 exact execute-address hardware breakpoints; no watchpoints" in booter
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for parameter in (
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".EXTENSION_A (1)",
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".EXTENSION_C (1)",
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".EXTENSION_M (1)",
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".EXTENSION_ZBA (1)",
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".EXTENSION_ZBB (1)",
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".EXTENSION_ZBC (1)",
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".EXTENSION_ZBKB (1)",
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".EXTENSION_ZBKX (1)",
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".EXTENSION_ZBS (1)",
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".EXTENSION_ZIFENCEI (1)",
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".EXTENSION_ZILSD (1)",
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".EXTENSION_XH3BEXTM (1)",
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".EXTENSION_XH3IRQ (1)",
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".U_MODE (0)",
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".PMP_REGIONS (0)",
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".BREAKPOINT_TRIGGERS(2)",
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".NUM_IRQS (30)",
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".IRQ_PRIORITY_BITS (2)",
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):
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assert parameter in management_core
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assert ".HAVE_SBA(0)" in management_debug
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assert "ahbl.htrans == AHBL_TRANS_NSEQ" in ahbl_to_axi4
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assert "axi4.awlen = 8'd0;" in ahbl_to_axi4
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assert "axi4.arlen = 8'd0;" in ahbl_to_axi4
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assert "axi4.awlock = `AXI4_LOCK_NORM;" in ahbl_to_axi4
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assert "axi4.arlock = `AXI4_LOCK_NORM;" in ahbl_to_axi4
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