mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
3131762b35
- Updated SRAM instance paths in to reflect new hierarchy. - Enhanced to include additional source files and updated parameterized tests for SRAM configurations. - Modified to align with new SRAM structure and added a test for stale macro hierarchy. - Introduced to validate dual-port local-memory protocol and CPU debug/reset functionality, including comprehensive simulation checks.
260 lines
11 KiB
Systemverilog
260 lines
11 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao
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// SPDX-License-Identifier: MulanPSL-2.0
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`include "mmap_define.svh"
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// Independent one-operation I/D frontends. AHB write data belongs to the cycle
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// following address acceptance. Local stores complete only after macro commit.
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// Only non-SRAM work enters the tagged, non-posted slow-path merge.
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module tiny_cpu_mem (
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input logic clk_i,
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input logic rst_n_i,
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input logic quiesce_i,
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output logic idle_o,
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ahbl_if.slave cpu [2],
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tiny_sram_port_if.master local_ports[2],
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axi4_if.master slow_axi4
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);
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typedef enum logic [2:0] {
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Idle,
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WriteCapture,
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LocalIssue,
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LocalWait,
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SlowIssue,
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SlowWait,
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ErrorFirst,
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ErrorLast
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} state_e;
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typedef struct packed {
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state_e state;
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logic [31:0] addr, data;
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logic [2:0] size;
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logic write;
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logic [3:0] strb;
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} request_t;
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request_t s_req_d[2], s_req_q[2];
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logic [1:0] s_terminal, s_err, s_slow_req, s_slow_grant, s_front_idle;
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logic s_slow_selected, s_slow_valid, s_slow_accept;
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typedef enum logic [1:0] {
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SlowIdle,
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SlowAddress,
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SlowData,
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SlowResponse
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} slow_state_e;
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typedef struct packed {
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slow_state_e state;
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logic owner, write, error;
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logic [2:0] size;
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logic [31:0] addr, data, rdata;
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} slow_t;
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slow_t s_slow_d, s_slow_q;
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ahbl_if u_slow_ahbl_if (
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.hclk (clk_i),
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.hresetn(rst_n_i)
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);
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axi4_if #(
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.ADDR_WIDTH(32),
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.DATA_WIDTH(32),
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.ID_WIDTH (1),
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.USER_WIDTH(1)
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) u_slow_axi4_if (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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logic s_adapter_idle;
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for (genvar port_index = 0; port_index < 2; port_index++) begin : gen_port
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assign s_slow_req[port_index] = s_req_q[port_index].state == SlowIssue;
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assign s_front_idle[port_index] = (s_req_q[port_index].state == Idle) &&
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(quiesce_i || !cpu[port_index].htrans[1]);
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assign s_err[port_index] = (s_req_q[port_index].state == ErrorFirst) ||
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(s_req_q[port_index].state == ErrorLast) ||
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((s_req_q[port_index].state == SlowWait) &&
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(s_slow_q.state == SlowResponse) && (s_slow_q.owner == 1'(port_index)) && s_slow_q.error);
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assign s_terminal[port_index] = (s_req_q[port_index].state == ErrorLast) ||
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((s_req_q[port_index].state == LocalWait) && local_ports[port_index].rsp_valid) ||
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((s_req_q[port_index].state == SlowWait) &&
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(s_slow_q.state == SlowResponse) && (s_slow_q.owner == 1'(port_index)) && !s_slow_q.error);
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assign cpu[port_index].hready =
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((s_req_q[port_index].state == Idle) && !quiesce_i) || s_terminal[port_index];
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assign cpu[port_index].hresp = s_err[port_index];
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assign cpu[port_index].hrdata = (s_req_q[port_index].state == LocalWait) ?
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local_ports[port_index].rdata : s_slow_q.rdata;
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assign local_ports[port_index].req_valid = s_req_q[port_index].state == LocalIssue;
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assign local_ports[port_index].addr = s_req_q[port_index].addr;
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assign local_ports[port_index].write = s_req_q[port_index].write;
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assign local_ports[port_index].wdata = s_req_q[port_index].data;
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assign local_ports[port_index].wstrb = s_req_q[port_index].strb;
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assign local_ports[port_index].rsp_ready = s_req_q[port_index].state == LocalWait;
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always_comb begin
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s_req_d[port_index] = s_req_q[port_index];
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unique case (s_req_q[port_index].state)
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WriteCapture: begin
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unique case (s_req_q[port_index].size)
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3'd0: begin
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s_req_d[port_index].data = {24'd0, cpu[port_index].hwdata[7:0]} <<
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(8 * s_req_q[port_index].addr[1:0]);
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s_req_d[port_index].strb = 4'b0001 << s_req_q[port_index].addr[1:0];
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end
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3'd1: begin
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s_req_d[port_index].data = {16'd0, cpu[port_index].hwdata[15:0]} <<
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(8 * s_req_q[port_index].addr[1:0]);
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s_req_d[port_index].strb = 4'b0011 << s_req_q[port_index].addr[1:0];
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end
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default: begin
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s_req_d[port_index].data = cpu[port_index].hwdata;
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s_req_d[port_index].strb = 4'b1111;
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end
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endcase
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s_req_d[port_index].state =
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`SOC_ADDR_IS_SRAM(s_req_q[port_index].addr)
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? LocalIssue : SlowIssue;
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end
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LocalIssue: if (local_ports[port_index].req_ready) s_req_d[port_index].state = LocalWait;
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SlowIssue:
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if (s_slow_accept && s_slow_grant[port_index]) s_req_d[port_index].state = SlowWait;
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SlowWait: if (s_err[port_index]) s_req_d[port_index].state = ErrorLast;
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ErrorFirst: s_req_d[port_index].state = ErrorLast;
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default: begin
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end
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endcase
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if (cpu[port_index].hready) begin
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s_req_d[port_index].state = Idle;
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// Capture even a terminal-cycle overlap during quiesce: that address
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// was acknowledged by HREADY and cannot be silently discarded.
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if (cpu[port_index].htrans[1]) begin
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s_req_d[port_index].addr = cpu[port_index].haddr;
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s_req_d[port_index].size = cpu[port_index].hsize;
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s_req_d[port_index].write = cpu[port_index].hwrite;
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s_req_d[port_index].strb = '0;
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if ((cpu[port_index].htrans != 2'b10) || cpu[port_index].hmastlock ||
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(cpu[port_index].hsize > 3'd2) ||
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((cpu[port_index].haddr & ((32'd1 << cpu[port_index].hsize) - 32'd1)) != 32'd0) ||
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((port_index == 0) && (cpu[port_index].hwrite || (cpu[port_index].hsize != 3'd2))))
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s_req_d[port_index].state = ErrorFirst;
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else if (cpu[port_index].hwrite) s_req_d[port_index].state = WriteCapture;
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else
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s_req_d[port_index].state =
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`SOC_ADDR_IS_SRAM(cpu[port_index].haddr)
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? LocalIssue : SlowIssue;
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end
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end
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end
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dffr #(
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.DATA_WIDTH($bits(request_t))
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) u_request (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_req_d[port_index]),
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.dat_o (s_req_q[port_index])
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);
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end
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assign idle_o = (&s_front_idle) && (s_slow_q.state == SlowIdle) && s_adapter_idle;
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assign s_slow_accept = (s_slow_q.state == SlowIdle) && s_slow_valid;
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round_robin_arbiter #(
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.CLIENTS(2)
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) u_slow_arbiter (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.advance_i (s_slow_accept),
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.request_i (s_slow_req),
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.grant_o (s_slow_grant),
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.selected_o(s_slow_selected),
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.valid_o (s_slow_valid)
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);
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always_comb begin
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s_slow_d = s_slow_q;
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unique case (s_slow_q.state)
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SlowIdle:
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if (s_slow_accept) begin
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s_slow_d.owner = s_slow_selected;
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s_slow_d.addr = s_req_q[s_slow_selected].addr;
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s_slow_d.write = s_req_q[s_slow_selected].write;
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s_slow_d.size = s_req_q[s_slow_selected].size;
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// The shared AHB adapter applies lane shifting itself.
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s_slow_d.data = s_req_q[s_slow_selected].data >> (8 * s_req_q[s_slow_selected].addr[1:0]);
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s_slow_d.state = SlowAddress;
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end
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SlowAddress: if (u_slow_ahbl_if.hready) s_slow_d.state = SlowData;
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SlowData:
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if (u_slow_ahbl_if.hready) begin
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s_slow_d.rdata = u_slow_ahbl_if.hrdata;
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s_slow_d.error = u_slow_ahbl_if.hresp;
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s_slow_d.state = SlowResponse;
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end
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SlowResponse: s_slow_d.state = SlowIdle;
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default: s_slow_d.state = SlowIdle;
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endcase
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end
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dffr #(
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.DATA_WIDTH($bits(slow_t))
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) u_slow_state (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_slow_d),
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.dat_o (s_slow_q)
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);
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assign u_slow_ahbl_if.haddr = s_slow_q.addr;
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assign u_slow_ahbl_if.hwrite = s_slow_q.write;
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assign u_slow_ahbl_if.hsize = s_slow_q.size;
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assign u_slow_ahbl_if.hwdata = s_slow_q.data;
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assign u_slow_ahbl_if.htrans = (s_slow_q.state == SlowAddress) ? 2'b10 : 2'b00;
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assign u_slow_ahbl_if.hburst = '0;
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assign u_slow_ahbl_if.hprot = {3'b001, s_slow_q.owner};
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assign u_slow_ahbl_if.hmastlock = 1'b0;
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ahbl2axi4 #(
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.TwoCycleErrors(1'b1)
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) u_slow_adapter (
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.ahbl (u_slow_ahbl_if),
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.axi4 (u_slow_axi4_if),
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.idle_o(s_adapter_idle)
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);
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// Forward every channel unchanged except the saved instruction attribute.
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// Tiny's fabric uses it to reject fetches before peripheral side effects.
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assign slow_axi4.awid = u_slow_axi4_if.awid;
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assign slow_axi4.awaddr = u_slow_axi4_if.awaddr;
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assign slow_axi4.awlen = u_slow_axi4_if.awlen;
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assign slow_axi4.awsize = u_slow_axi4_if.awsize;
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assign slow_axi4.awburst = u_slow_axi4_if.awburst;
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assign slow_axi4.awlock = u_slow_axi4_if.awlock;
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assign slow_axi4.awcache = u_slow_axi4_if.awcache;
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assign slow_axi4.awprot = {!s_slow_q.owner, u_slow_axi4_if.awprot[1:0]};
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assign slow_axi4.awqos = u_slow_axi4_if.awqos;
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assign slow_axi4.awregion = u_slow_axi4_if.awregion;
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assign slow_axi4.awuser = u_slow_axi4_if.awuser;
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assign slow_axi4.awvalid = u_slow_axi4_if.awvalid;
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assign slow_axi4.arid = u_slow_axi4_if.arid;
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assign slow_axi4.araddr = u_slow_axi4_if.araddr;
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assign slow_axi4.arlen = u_slow_axi4_if.arlen;
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assign slow_axi4.arsize = u_slow_axi4_if.arsize;
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assign slow_axi4.arburst = u_slow_axi4_if.arburst;
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assign slow_axi4.arlock = u_slow_axi4_if.arlock;
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assign slow_axi4.arcache = u_slow_axi4_if.arcache;
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assign slow_axi4.arprot = {!s_slow_q.owner, u_slow_axi4_if.arprot[1:0]};
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assign slow_axi4.arqos = u_slow_axi4_if.arqos;
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assign slow_axi4.arregion = u_slow_axi4_if.arregion;
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assign slow_axi4.aruser = u_slow_axi4_if.aruser;
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assign slow_axi4.arvalid = u_slow_axi4_if.arvalid;
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assign slow_axi4.wdata = u_slow_axi4_if.wdata;
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assign slow_axi4.wstrb = u_slow_axi4_if.wstrb;
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assign slow_axi4.wlast = u_slow_axi4_if.wlast;
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assign slow_axi4.wuser = u_slow_axi4_if.wuser;
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assign slow_axi4.wvalid = u_slow_axi4_if.wvalid;
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assign slow_axi4.rready = u_slow_axi4_if.rready;
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assign slow_axi4.bready = u_slow_axi4_if.bready;
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assign u_slow_axi4_if.awready = slow_axi4.awready;
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assign u_slow_axi4_if.arready = slow_axi4.arready;
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assign u_slow_axi4_if.wready = slow_axi4.wready;
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assign u_slow_axi4_if.rvalid = slow_axi4.rvalid;
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assign u_slow_axi4_if.rid = slow_axi4.rid;
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assign u_slow_axi4_if.rdata = slow_axi4.rdata;
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assign u_slow_axi4_if.rresp = slow_axi4.rresp;
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assign u_slow_axi4_if.rlast = slow_axi4.rlast;
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assign u_slow_axi4_if.ruser = slow_axi4.ruser;
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assign u_slow_axi4_if.bvalid = slow_axi4.bvalid;
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assign u_slow_axi4_if.bid = slow_axi4.bid;
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assign u_slow_axi4_if.bresp = slow_axi4.bresp;
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assign u_slow_axi4_if.buser = slow_axi4.buser;
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endmodule
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