mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
3131762b35
- Updated SRAM instance paths in to reflect new hierarchy. - Enhanced to include additional source files and updated parameterized tests for SRAM configurations. - Modified to align with new SRAM structure and added a test for stale macro hierarchy. - Introduced to validate dual-port local-memory protocol and CPU debug/reset functionality, including comprehensive simulation checks.
233 lines
9.9 KiB
Systemverilog
233 lines
9.9 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao
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// SPDX-License-Identifier: MulanPSL-2.0
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// One external transaction per group. Address ownership lasts through the
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// terminal response, but the macro is arbitrated separately for every beat.
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// W may precede AW on the bus; it is backpressured until its AW is accepted.
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module tiny_sram_axi4 #(
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parameter logic [31:0] GroupBase = 32'h3000_0000
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) (
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input logic clk_i,
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input logic rst_n_i,
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axi4_if.slave axi4,
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tiny_sram_port_if.master memory
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);
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typedef enum logic [2:0] {
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Idle,
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ReadStream,
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ReadError,
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WriteStream,
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WriteResponse,
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WriteDrain
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} state_e;
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typedef struct packed {
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state_e state;
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logic prefer_write;
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logic id;
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logic [31:0] addr;
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logic [7:0] len, beat;
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logic [2:0] size;
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logic [1:0] burst, resp;
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logic [8:0] issued, completed;
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logic last;
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} transaction_t;
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typedef struct packed {
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logic [31:0] addr, data;
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logic [3:0] strb;
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} write_t;
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transaction_t s_transaction_d, s_transaction_q;
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write_t s_write_input, s_write_output;
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logic [31:0] s_next_addr;
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logic [1:0] s_ar_resp, s_aw_resp;
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logic [3:0] s_lane_mask;
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logic s_expected_last, s_write_legal;
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logic s_write_full, s_write_empty, s_write_push, s_write_pop;
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logic s_req_accept, s_resp_accept, s_write_accept;
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function automatic logic [1:0] address_response(input logic [31:0] addr_i,
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input logic [7:0] len_i, input logic [2:0] size_i,
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input logic [1:0] burst_i, input logic lock_i);
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logic [32:0] bytes_count, last_addr;
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logic wrap_legal;
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bytes_count = ({25'd0, len_i} + 33'd1) << size_i;
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wrap_legal = (len_i == 8'd1) || (len_i == 8'd3) || (len_i == 8'd7) || (len_i == 8'd15);
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last_addr = {1'b0, addr_i} + bytes_count - 33'd1;
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if (burst_i == 2'b00) last_addr = {1'b0, addr_i} + (33'd1 << size_i) - 33'd1;
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if (burst_i == 2'b10)
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last_addr = ({1'b0, addr_i} & ~(bytes_count - 33'd1)) + bytes_count - 33'd1;
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if (lock_i || (len_i > 8'd15) || (size_i > 3'd2) ||
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(burst_i == 2'b11) || ((burst_i == 2'b10) && !wrap_legal) ||
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((addr_i & ((32'd1 << size_i) - 32'd1)) != 32'd0) || last_addr[32] ||
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(addr_i[31:12] != last_addr[31:12]))
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return 2'b10;
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if ((addr_i < GroupBase) || (last_addr[31:0] > (GroupBase + 32'h7fff))) return 2'b11;
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return 2'b00;
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endfunction
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assign s_ar_resp = address_response(
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axi4.araddr, axi4.arlen, axi4.arsize, axi4.arburst, axi4.arlock
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);
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assign s_aw_resp = address_response(
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axi4.awaddr, axi4.awlen, axi4.awsize, axi4.awburst, axi4.awlock
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);
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assign axi4.arready = (s_transaction_q.state == Idle) &&
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!(s_transaction_q.prefer_write && axi4.awvalid);
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assign axi4.awready = (s_transaction_q.state == Idle) &&
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(s_transaction_q.prefer_write || !axi4.arvalid);
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assign axi4.wready = ((s_transaction_q.state == WriteStream) && !s_transaction_q.last &&
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(!s_write_full || s_write_pop)) || (s_transaction_q.state == WriteDrain);
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assign axi4.rvalid = (s_transaction_q.state == ReadError) ||
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((s_transaction_q.state == ReadStream) && memory.rsp_valid);
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assign axi4.rid = s_transaction_q.id;
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assign axi4.rdata = (s_transaction_q.state == ReadStream) ? memory.rdata : 32'd0;
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assign axi4.rresp = s_transaction_q.resp;
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assign axi4.rlast = s_transaction_q.beat == s_transaction_q.len;
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assign axi4.ruser = '0;
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assign axi4.bvalid = s_transaction_q.state == WriteResponse;
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assign axi4.bid = s_transaction_q.id;
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assign axi4.bresp = s_transaction_q.resp;
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assign axi4.buser = '0;
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// Read responses stay in the group's reserved queue until R handshakes.
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// Issuance and retirement have independent positions within the same burst.
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assign memory.req_valid = ((s_transaction_q.state == ReadStream) &&
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(s_transaction_q.issued <= {1'b0, s_transaction_q.len})) ||
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((s_transaction_q.state == WriteStream) && !s_write_empty);
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assign memory.addr = memory.write ? s_write_output.addr : s_transaction_q.addr;
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assign memory.write = s_transaction_q.state == WriteStream;
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assign memory.wdata = s_write_output.data;
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assign memory.wstrb = s_write_output.strb;
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assign memory.rsp_ready = ((s_transaction_q.state == ReadStream) && axi4.rready) ||
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(s_transaction_q.state == WriteStream);
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assign s_req_accept = memory.req_valid && memory.req_ready;
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assign s_resp_accept = memory.rsp_valid && memory.rsp_ready;
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assign s_write_accept = axi4.wvalid && axi4.wready;
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assign s_write_push = (s_transaction_q.state == WriteStream) && s_write_accept && s_write_legal;
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assign s_write_pop = (s_transaction_q.state == WriteStream) && s_req_accept;
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assign s_write_input = {s_transaction_q.addr, axi4.wdata, axi4.wstrb};
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// Capture W before it becomes eligible at the macro. A full queue can
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// replace its head on the same edge that the arbiter commits that word.
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fifo #(
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.DATA_WIDTH ($bits(write_t)),
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.BUFFER_DEPTH(2)
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) u_write_fifo (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.flush_i(1'b0),
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.push_i (s_write_push),
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.full_o (s_write_full),
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.dat_i (s_write_input),
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.pop_i (s_write_pop),
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.empty_o(s_write_empty),
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.dat_o (s_write_output),
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.cnt_o () // Full/empty and accepted/completed counts cover ownership.
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);
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assign s_lane_mask = 4'(((32'd1 << (32'd1 << s_transaction_q.size)) - 32'd1)
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<< s_transaction_q.addr[1:0]);
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assign s_expected_last = s_transaction_q.beat == s_transaction_q.len;
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assign s_write_legal = ((axi4.wstrb & ~s_lane_mask) == 4'd0) && (axi4.wlast == s_expected_last);
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axi4_addr_gen #(
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.ADDR_WIDTH(32)
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) u_address (
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.alen_i (s_transaction_q.len),
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.asize_i (s_transaction_q.size),
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.aburst_i(s_transaction_q.burst),
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.addr_i (s_transaction_q.addr),
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.addr_o (s_next_addr)
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);
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always_comb begin
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s_transaction_d = s_transaction_q;
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unique case (s_transaction_q.state)
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Idle: begin
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s_transaction_d.beat = '0;
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s_transaction_d.issued = '0;
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s_transaction_d.completed = '0;
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s_transaction_d.last = 1'b0;
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if (axi4.arvalid && axi4.arready) begin
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s_transaction_d.prefer_write = 1'b1;
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s_transaction_d.id = axi4.arid;
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s_transaction_d.addr = axi4.araddr;
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// Match the shared target's malformed-address error response length.
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s_transaction_d.len = (s_ar_resp == 2'b10) ? 8'd0 : axi4.arlen;
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s_transaction_d.size = axi4.arsize;
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s_transaction_d.burst = axi4.arburst;
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s_transaction_d.resp = s_ar_resp;
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s_transaction_d.state = (s_ar_resp == 2'b00) ? ReadStream : ReadError;
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end else if (axi4.awvalid && axi4.awready) begin
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s_transaction_d.prefer_write = 1'b0;
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s_transaction_d.id = axi4.awid;
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s_transaction_d.addr = axi4.awaddr;
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s_transaction_d.len = (s_aw_resp == 2'b10) ? 8'd0 : axi4.awlen;
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s_transaction_d.size = axi4.awsize;
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s_transaction_d.burst = axi4.awburst;
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s_transaction_d.resp = s_aw_resp;
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s_transaction_d.state = (s_aw_resp == 2'b00) ? WriteStream : WriteDrain;
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end
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end
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ReadStream: begin
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if (s_req_accept) begin
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s_transaction_d.issued = s_transaction_q.issued + 9'd1;
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s_transaction_d.addr = s_next_addr;
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end
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if (s_resp_accept) begin
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s_transaction_d.completed = s_transaction_q.completed + 9'd1;
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if (axi4.rlast) s_transaction_d.state = Idle;
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else s_transaction_d.beat = s_transaction_q.beat + 8'd1;
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end
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end
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ReadError:
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if (axi4.rready) begin
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if (axi4.rlast) s_transaction_d.state = Idle;
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else s_transaction_d.beat = s_transaction_q.beat + 8'd1;
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end
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WriteStream: begin
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if (s_write_accept) begin
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s_transaction_d.last = s_expected_last || axi4.wlast;
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s_transaction_d.beat = s_transaction_q.beat + 8'd1;
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s_transaction_d.addr = s_next_addr;
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if (!s_write_legal) s_transaction_d.resp = 2'b10;
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end
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if (s_req_accept) s_transaction_d.issued = s_transaction_q.issued + 9'd1;
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if (s_resp_accept) s_transaction_d.completed = s_transaction_q.completed + 9'd1;
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// Errors do not discard older queued writes. B acknowledges all
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// accepted legal beats only after their macro-commit responses drain.
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if (s_transaction_q.last && s_write_empty &&
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(s_transaction_q.issued == s_transaction_q.completed))
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s_transaction_d.state = WriteResponse;
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end
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WriteDrain:
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if (axi4.wvalid) begin
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if (s_expected_last || axi4.wlast) s_transaction_d.state = WriteResponse;
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else s_transaction_d.beat = s_transaction_q.beat + 8'd1;
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end
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WriteResponse: if (axi4.bready) s_transaction_d.state = Idle;
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default: s_transaction_d.state = Idle;
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endcase
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end
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dffr #(
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.DATA_WIDTH($bits(transaction_t))
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) u_transaction (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_transaction_d),
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.dat_o (s_transaction_q)
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);
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`ifdef HAVE_SVA
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assert property (@(posedge clk_i) disable iff (!rst_n_i)
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s_transaction_q.completed <= s_transaction_q.issued);
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assert property (@(posedge clk_i) disable iff (!rst_n_i)
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axi4.bvalid |-> s_write_empty &&
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(s_transaction_q.completed == s_transaction_q.issued));
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assert property (@(posedge clk_i) disable iff (!rst_n_i)
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axi4.rvalid && !axi4.rready |=> axi4.rvalid &&
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$stable(
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{axi4.rdata, axi4.rid, axi4.rresp, axi4.rlast}
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));
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assert property (@(posedge clk_i) disable iff (!rst_n_i)
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axi4.bvalid && !axi4.bready |=> axi4.bvalid && $stable(
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{axi4.bid, axi4.bresp}
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));
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`endif
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endmodule
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