maksyuki
31daf3e84c
Integrate the SPI-P2 shared-DMA ABI into the Tiny product: SPI0 at 0x1001D000 with IRQ25 and RCU target16, the four frozen Gen1 ALT routes, latched four-bit source qualification through the fabric and APB CDC, GPIO readiness/ownership guard, and the bounded rs_spi_* HAL with the TINY_SPI_P3_ACCEPTANCE ci_smoke image. Tiny DMA enables V2.2 requests 16/17 with exact fixed FIFO MMIO checks; Mini remains default-disabled and unchanged. Review closure: the DMA AXI4 master stages the origin channel with each burst so final and contended SPI alias bursts stay qualified, the RCU spare feedback bit is tied off for four-state simulators, and the clock-switch quiescence now includes the SPI session. Validation: full Pytest 2097 passed, 0 failed, 1 skipped (optional pypdf); both Tiny profiles pass the SPI-P3 Verilator acceptance (SIM_TEST_PASS cycles=1030088); R2-P7 Verilator acceptance, Mini DMA formal prove and cover, Mini/Tiny lint, Tiny Yosys synthesis, netsim-boot and OpenSTA pass; C format/policy/host tests and RTL format/style checks clean. Evidence and remaining obligations are recorded in docs/ip/spi-verification.md. Tiny Icarus behavioral remains blocked by the pre-existing observer/sv2v defect (routed to the R2 DV owners); Mini smoke synthesis host timeout is skipped per maintainer decision. Human phase acceptance and SPI-P4/P5 remain outstanding; phase_accepted stays false.
1.4 KiB
SPI-P3 Tiny GPIO RCU and SDK Integration
SPI-P3 binds the accepted SPI-P2 shared-DMA ABI to the Tiny product. It adds the frozen APB, IRQ25, RCU target16 and four Gen1 routes while preserving the QFN64 package, existing GPIO ownership, DMA channels and legacy XPI LCD path.
Tiny internal AXI transactions carry a private four-bit source marker. Fabric
admission rewrites the owner marker, the APB/CDC bridges retain it through the
terminal response, and SPI accepts DMA aliases only for a qualified central
DMA channel. CPU and other-owner accesses cannot use DMA aliases. SPI DMA
requests are fixed to 0x1001D054 (TX) and 0x1001D058 (RX).
GPIO readiness combines USER_SELECT, handoff, ALT/electrical state and the Tiny lifecycle reset. Raw GPIO30 input feeds MISO directly; the ordinary GPIO filter path is not used for SPI sampling. GPIO and SPI gate/reset operations remain blocked while a PIO user claim or latched SPI session is active.
The freestanding rs_spi_* HAL performs capability discovery, bounded
configuration, acquire/release, CPU segments, status and recovery. It does not
add a display adapter; display and snapshot application work remain SPI-P4.
Focused P3 records belong under build/<variant>/meta/spi-p3/. Tiny acceptance
requires command success, TEST_STATUS/SIM_TEST_PASS and no forbidden error
marker. phase_accepted remains false until human review. Pre-final STA is
observational; SPI-P5 remains the final physical qualification phase.