mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
31daf3e84c
Integrate the SPI-P2 shared-DMA ABI into the Tiny product: SPI0 at 0x1001D000 with IRQ25 and RCU target16, the four frozen Gen1 ALT routes, latched four-bit source qualification through the fabric and APB CDC, GPIO readiness/ownership guard, and the bounded rs_spi_* HAL with the TINY_SPI_P3_ACCEPTANCE ci_smoke image. Tiny DMA enables V2.2 requests 16/17 with exact fixed FIFO MMIO checks; Mini remains default-disabled and unchanged. Review closure: the DMA AXI4 master stages the origin channel with each burst so final and contended SPI alias bursts stay qualified, the RCU spare feedback bit is tied off for four-state simulators, and the clock-switch quiescence now includes the SPI session. Validation: full Pytest 2097 passed, 0 failed, 1 skipped (optional pypdf); both Tiny profiles pass the SPI-P3 Verilator acceptance (SIM_TEST_PASS cycles=1030088); R2-P7 Verilator acceptance, Mini DMA formal prove and cover, Mini/Tiny lint, Tiny Yosys synthesis, netsim-boot and OpenSTA pass; C format/policy/host tests and RTL format/style checks clean. Evidence and remaining obligations are recorded in docs/ip/spi-verification.md. Tiny Icarus behavioral remains blocked by the pre-existing observer/sv2v defect (routed to the R2 DV owners); Mini smoke synthesis host timeout is skipped per maintainer decision. Human phase acceptance and SPI-P4/P5 remain outstanding; phase_accepted stays false.
124 lines
4.5 KiB
Systemverilog
124 lines
4.5 KiB
Systemverilog
// Standalone SPI shell. DMA pacing is local; product route and fabric origin remain external.
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module apb4_spi #(
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parameter bit EnableDma = 1'b1
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) (
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input logic clk_i,
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rst_n_i,
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input logic [31:0] clock_hz_i,
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input logic [ 1:0] origin_i,
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input logic [ 4:0] request_i,
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input logic [ 2:0] channel_i,
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input logic [ 1:0] credit_valid_i,
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credit_retire_i,
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input logic [ 3:0] dma_status_i,
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input logic [ 1:0] dma_start_pending_i,
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input logic dma_error_i,
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input logic [31:0] user_select_i,
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handoff_i,
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alt_enable_i,
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alt_select_i,
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input logic [31:0] output_enable_i,
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open_drain_i,
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input logic gpio_ready_i,
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miso_i,
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output logic sck_o,
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mosi_o,
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cs_n_o,
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output_enable_o,
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irq_o,
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session_owned_o,
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lifecycle_idle_o,
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output logic [ 1:0] credit_commit_o,
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apb4_if.slave apb4
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);
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spi_ctrl_if u_ctrl ();
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spi_pkg::configuration_t s_cfg;
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spi_pkg::status_t s_stat;
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logic [31:0] s_claim, s_ready;
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logic s_handback, s_credit_fault, s_reg_credit_fault, s_pacing_fault;
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logic s_fifo_pending;
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logic [1:0] s_credit_pending, s_pacing_pending, s_reg_credit_pending;
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logic [1:0] s_credit_valid, s_credit_retire, s_credit_commit;
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logic [3:0] s_dma_stat;
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logic s_unused;
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assign s_cfg = u_ctrl.cfg;
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assign s_stat = u_ctrl.stat;
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// Only personality bits feed the GPIO guard; other fields feed the core/reg blocks.
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assign s_unused = ^s_cfg;
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assign s_credit_fault = s_reg_credit_fault | s_pacing_fault;
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assign s_credit_pending = s_pacing_pending | s_reg_credit_pending;
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spi_dma_pacing u_dma_pacing (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.enable_i (EnableDma),
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.tx_binding_i (s_cfg.tx_binding),
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.rx_binding_i (s_cfg.rx_binding),
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.dma_start_pending_i(dma_start_pending_i),
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.dma_status_i (dma_status_i),
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.dma_error_i (dma_error_i),
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.credit_valid_i (credit_valid_i),
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.credit_retire_i (credit_retire_i),
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.credit_commit_i (s_credit_commit),
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.credit_valid_o (s_credit_valid),
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.credit_retire_o (s_credit_retire),
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.credit_pending_o (s_pacing_pending),
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.dma_status_o (s_dma_stat),
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.credit_fault_o (s_pacing_fault),
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.busy_o ()
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);
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spi_gpio_guard u_gpio_guard (
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.session_i (s_cfg.session),
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.user_select_i (user_select_i),
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.handoff_i (handoff_i),
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.alt_enable_i (alt_enable_i),
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.alt_select_i (alt_select_i),
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.output_enable_i(output_enable_i),
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.open_drain_i (open_drain_i),
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.gpio_ready_i (gpio_ready_i),
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.claim_o (s_claim),
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.ready_o (s_ready),
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.handback_o (s_handback)
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);
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spi_reg u_reg (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.clock_hz_i (clock_hz_i),
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.origin_i (origin_i),
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.request_i (request_i),
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.channel_i (channel_i),
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.credit_valid_i (s_credit_valid),
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.credit_retire_i (s_credit_retire),
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.dma_status_i (s_dma_stat),
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.dma_start_pending_i(dma_start_pending_i),
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.credit_commit_o (s_credit_commit),
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.credit_pending_o (s_reg_credit_pending),
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.fifo_pending_o (s_fifo_pending),
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.credit_fault_o (s_reg_credit_fault),
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.irq_o (irq_o),
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.apb4 (apb4),
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.ctrl (u_ctrl)
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);
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assign credit_commit_o = s_credit_commit;
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assign session_owned_o = s_stat.status[5];
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assign lifecycle_idle_o = s_stat.status[10] && s_stat.status[11] && !s_stat.status[5];
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spi_master_core u_master_core (
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.apb_pending_i (s_fifo_pending),
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.claim_i (s_claim),
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.ready_pins_i (s_ready),
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.gpio_ready_i (gpio_ready_i),
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.handback_i (s_handback),
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.dma_status_i (s_dma_stat),
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.dma_start_pending_i(dma_start_pending_i),
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.dma_error_i (dma_error_i),
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.credit_fault_i (s_credit_fault),
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.miso_i (miso_i),
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.sck_o (sck_o),
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.mosi_o (mosi_o),
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.cs_n_o (cs_n_o),
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.output_enable_o (output_enable_o),
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.ctrl (u_ctrl)
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);
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endmodule
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