mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
31daf3e84c
Integrate the SPI-P2 shared-DMA ABI into the Tiny product: SPI0 at 0x1001D000 with IRQ25 and RCU target16, the four frozen Gen1 ALT routes, latched four-bit source qualification through the fabric and APB CDC, GPIO readiness/ownership guard, and the bounded rs_spi_* HAL with the TINY_SPI_P3_ACCEPTANCE ci_smoke image. Tiny DMA enables V2.2 requests 16/17 with exact fixed FIFO MMIO checks; Mini remains default-disabled and unchanged. Review closure: the DMA AXI4 master stages the origin channel with each burst so final and contended SPI alias bursts stay qualified, the RCU spare feedback bit is tied off for four-state simulators, and the clock-switch quiescence now includes the SPI session. Validation: full Pytest 2097 passed, 0 failed, 1 skipped (optional pypdf); both Tiny profiles pass the SPI-P3 Verilator acceptance (SIM_TEST_PASS cycles=1030088); R2-P7 Verilator acceptance, Mini DMA formal prove and cover, Mini/Tiny lint, Tiny Yosys synthesis, netsim-boot and OpenSTA pass; C format/policy/host tests and RTL format/style checks clean. Evidence and remaining obligations are recorded in docs/ip/spi-verification.md. Tiny Icarus behavioral remains blocked by the pre-existing observer/sv2v defect (routed to the R2 DV owners); Mini smoke synthesis host timeout is skipped per maintainer decision. Human phase acceptance and SPI-P4/P5 remain outstanding; phase_accepted stays false.
497 lines
16 KiB
JSON
497 lines
16 KiB
JSON
{
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"schema_version": 2,
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"external_fabric": {
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"phase": "TINY-R2-P7",
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"clock_domain": "system",
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"target_controllers": "u_soc.u_fabric.gen_target[%d].u_controller",
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"target_count": 29,
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"apb_bridges": "SYS frontends; acknowledged per-endpoint crossings to AON, PCLK and MEM",
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"fabric_reset": "fabric leaf; target reset blocks admission and aborts accepted target work with DECERR",
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"hart_reset": "CPU-only accepted-work drain; DMA and all target responses stay active",
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"runtime_peripheral_reset": "RCU blocks admissions, drains accepted work, holds reset for five local edges, waits for local release and bus barriers"
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},
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"local_memory": {
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"phase": "TINY-R2-P4",
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"clock_domain": "system",
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"cpu_instance": "u_soc.u_cpu.u_hazard3_cpu_2port",
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"frontend_instance": "u_soc.u_cpu_mem",
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"macro_instance": "u_soc.u_sram.gen_group[{group}].u_group.gen_bank[{bank}].u_ram.u_mem",
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"groups": 4,
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"macros_per_group": 8,
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"hart_reset": "halt then drain accepted I/D and slow responses; SRAM/DMA stay active",
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"main_sram_payload_reset": "none",
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"local_uncontended_max_cycles": 3
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},
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"reset_ports": [
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"ext_rst_n_i_pad",
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"jtag_trst_n_i_pad"
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],
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"domains": [
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{
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"name": "aon",
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"clock": "s_ref_clk",
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"reset": "ref_rst_n_o",
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"reset_source": "rst_n_i",
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"reset_primitive": "rst_sync",
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"path": "rtl/tiny/top/tiny_clock_reset_subsystem.sv",
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"instance": "u_ref_rst",
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"sta": {
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"source_port": "extclk_i_pad",
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"pin": "u_clock_buffer/clk_o",
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"period_ns": 41.666666667,
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"async_group": "core"
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}
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},
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{
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"name": "system",
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"clock": "s_backend_sys_clk",
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"reset": "system_rst_n_o",
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"reset_source": "s_system_req_n",
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"reset_primitive": "rst_sync",
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"path": "rtl/tiny/top/tiny_reset_tree.sv",
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"instance": "u_system_rst_sync",
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"sta": {
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"source_domain": "aon",
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"pin": "u_soc.u_clock_backend.u_sys_mux/clk_o",
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"period_ns": 41.666666667,
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"async_group": "core"
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}
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},
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{
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"name": "memory",
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"clock": "s_backend_mem_clk",
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"reset": "s_backend_mem_rst_n",
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"reset_source": "rst_n_i",
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"reset_primitive": "rst_sync",
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"path": "rtl/tiny/top/tiny_clock_reset_subsystem.sv",
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"instance": "u_mem_rst",
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"sta": {
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"source_domain": "system",
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"pin": "u_soc.u_clock_backend.u_mem_mux/clk_o",
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"period_ns": 41.666666667,
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"async_group": "core"
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}
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},
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{
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"name": "peripheral",
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"clock": "s_backend_pclk",
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"reset": "pclk_rst_n_o",
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"reset_source": "rst_n_i",
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"reset_primitive": "rst_sync",
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"path": "rtl/tiny/top/tiny_clock_reset_subsystem.sv",
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"instance": "u_pclk_rst",
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"sta": {
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"source_domain": "system",
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"pin": "u_soc.u_clock_backend.u_pclk_mux/clk_o",
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"period_ns": 41.666666667,
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"async_group": "core"
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}
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},
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{
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"name": "jtag",
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"clock": "s_jtag_tck_buf",
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"reset": "s_jtag_trst_n_sync",
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"reset_source": "jtag_trst_n_i",
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"reset_primitive": "rst_sync",
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"path": "rtl/ip/core/mgmt_debug_wrapper.sv",
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"instance": "u_jtag_rst_sync",
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"sta": {
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"source_port": "jtag_tck_i_pad",
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"object_type": "port",
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"period_ns": 100,
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"async_group": "jtag"
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}
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},
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{
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"name": "audio",
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"clock": "s_audio_clk",
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"reset": "s_audio_rst_n",
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"reset_source": "s_i2s_rst_n",
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"reset_primitive": "rst_sync",
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"path": "rtl/tiny/top/retrosoc_tiny.sv",
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"instance": "u_audio_rst_sync",
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"sta": {
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"source_port": "gpio_17_io_pad",
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"pin": "u_soc.u_audio_clock_buffer/clk_o",
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"period_ns": 54.253472222,
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"async_group": "audio"
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}
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},
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{
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"name": "dvp_pixel",
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"clock": "dvp_pixel_clk",
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"reset": "dvp_pixel_rst_n",
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"reset_source": "gpio_20_io_pad",
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"reset_primitive": "rst_sync",
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"path": "rtl/ip/multimedia/axi4s_dvp.sv",
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"instance": "u_dvp_pclk_rst_sync",
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"sta": {
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"source_port": "gpio_20_io_pad",
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"object_type": "port",
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"period_ns": 83.333333333,
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"async_group": "dvp_pixel"
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}
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}
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],
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"reset_distribution": {
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"release_edges": 5,
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"por": "u_soc.u_reset_tree.u_por_rst_sync",
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"system": "u_soc.u_reset_tree.u_system_rst_sync",
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"system_source": "por_rst_n_o && !watchdog_reset_req_i && backend_reset_n_i",
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"leaf_instance_pattern": "u_soc.u_reset_tree.gen_leaf[%d].u_leaf_rst_sync",
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"leaf_names": [
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"fabric",
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"gpio",
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"uart0",
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"timer0",
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"timer1",
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"i2c0",
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"xpi",
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"dma",
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"sysctrl",
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"clint",
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"sram",
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"archinfo",
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"pwm",
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"rtc",
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"wdg",
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"rng",
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"crc",
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"ws2812",
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"crypto",
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"i2s",
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"sdio",
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"dvp",
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"spi"
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],
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"cpu_prerequisite": "all global leaf resets and actual APB/DMA/XPI/RCU barriers; boot readiness latches until the next system reset",
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"hart": "u_soc.u_cpu.u_mgmt_debug_wrapper.u_mgmt_debug_reset.u_core_rst_sync",
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"jtag": "u_soc.u_cpu.u_mgmt_debug_wrapper.u_jtag_rst_sync",
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"dmi": "u_soc.u_cpu.u_mgmt_debug_wrapper.u_dmi_rst_sync",
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"watchdog_functional_reset": "REF24 five-edge release after backend retains the watchdog reset event; PCLK APB uses the wdg leaf",
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"main_sram_payload_reset": "none",
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"crypto": "six private macro banks; reset invalidates then scrubs/readbacks; CPU does not wait for READY",
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"clock_domain": "domain-specific",
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"peripheral": "tiny_peripheral_leaf; five running hold edges and five release edges; I2S additionally requires actual audio-side barrier readiness"
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},
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"crossings": [
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{
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"name": "debug_pclk_status",
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"source": "system", "destination": "peripheral", "primitive": "cdc_sync",
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"path": "rtl/tiny/top/retrosoc_tiny.sv", "instance": "u_debug_pclk_sync"
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},
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{
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"name": "debug_aon_status",
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"source": "system", "destination": "aon", "primitive": "cdc_sync",
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"path": "rtl/tiny/top/retrosoc_tiny.sv", "instance": "u_debug_ref_sync"
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},
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{
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"name": "rtc_wake",
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"source": "aon", "destination": "system", "primitive": "cdc_sync",
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"path": "rtl/tiny/top/retrosoc_tiny.sv", "instance": "u_rtc_wake_sync"
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},
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{
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"name": "hart_reset_event",
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"source": "system", "destination": "aon", "primitive": "cdc_2phase",
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"path": "rtl/tiny/top/retrosoc_tiny.sv", "instance": "u_hart_event_cdc"
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},
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{
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"name": "peripheral_interrupts",
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"source": "peripheral", "destination": "system", "primitive": "cdc_sync",
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"path": "rtl/tiny/top/retrosoc_tiny.sv", "instance": "u_irq_sync",
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"notes": "sticky interrupt levels; this vector also contains AON/MEM and synchronous SYS bits"
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},
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{
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"name": "wfi_permission",
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"source": "aon", "destination": "system", "primitive": "cdc_sync",
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"path": "rtl/tiny/top/retrosoc_tiny.sv", "instance": "u_wfi_gate_sync"
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},
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{
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"name": "admission_block_system",
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"source": "aon", "destination": "system", "primitive": "cdc_sync",
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"path": "rtl/tiny/top/retrosoc_tiny.sv", "instance": "u_block_sys"
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},
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{
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"name": "admission_block_dma",
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"source": "aon", "destination": "peripheral", "primitive": "cdc_sync",
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"path": "rtl/tiny/top/retrosoc_tiny.sv", "instance": "u_block_pclk"
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},
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{
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"name": "gate_reset_disabled",
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"source": "aon", "destination": "system", "primitive": "cdc_sync",
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"path": "rtl/tiny/top/retrosoc_tiny.sv", "instance": "u_disabled_sync"
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},
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{
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"name": "peripheral_idle",
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"source": "peripheral", "destination": "aon", "primitive": "cdc_sync",
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"path": "rtl/tiny/top/retrosoc_tiny.sv", "instance": "u_periph_idle_sync"
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},
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{
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"name": "xpi_idle",
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"source": "memory", "destination": "aon", "primitive": "cdc_sync",
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"path": "rtl/tiny/top/retrosoc_tiny.sv", "instance": "u_xpi_idle_sync"
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},
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{
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"name": "dma_ready",
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"source": "peripheral", "destination": "system", "primitive": "cdc_sync",
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"path": "rtl/tiny/top/retrosoc_tiny.sv", "instance": "u_dma_ready_sync"
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},
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{
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"name": "dma_retirement",
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"source": "peripheral", "destination": "system", "primitive": "cdc_sync",
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"path": "rtl/tiny/top/retrosoc_tiny.sv", "instance": "u_dma_idle_sync"
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},
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{
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"name": "fabric_retirement",
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"source": "system", "destination": "aon", "primitive": "cdc_sync",
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"path": "rtl/tiny/top/retrosoc_tiny.sv", "instance": "u_bus_idle_ref"
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},
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{
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"name": "gate_acknowledgements",
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"source": "peripheral", "destination": "aon", "primitive": "cdc_sync",
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"path": "rtl/tiny/top/retrosoc_tiny.sv", "instance": "u_gate_feedback"
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},
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{
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"name": "reset_hold_acknowledgements",
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"source": "peripheral", "destination": "aon", "primitive": "cdc_sync",
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"path": "rtl/tiny/top/retrosoc_tiny.sv", "instance": "u_held_feedback"
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},
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{
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"name": "reset_release_acknowledgements",
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"source": "system", "destination": "aon", "primitive": "cdc_sync",
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"path": "rtl/tiny/top/retrosoc_tiny.sv", "instance": "u_ready_feedback"
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},
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{
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"name": "debug_dmi",
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"source": "jtag",
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"destination": "system",
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"primitive": "hazard3_apb_async_bridge",
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"path": "rtl/managed/hazard3/hdl/debug/dtm/hazard3_jtag_dtm_core.v",
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"instance": "inst_hazard3_apb_async_bridge"
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},
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{
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"name": "xpi_mem_axi",
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"source": "system",
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"destination": "memory",
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"primitive": "tiny_axi4_async_bridge",
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"path": "rtl/tiny/top/retrosoc_tiny.sv",
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"instance": "u_xpi_mem_cdc",
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"source_reset": "s_fabric_rst_n",
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"destination_reset": "s_xpi_rst_n",
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"reset_semantics": "five-edge link release; source-owned held responses survive destination reset; drain remaining W before B and synthesize only missing R beats with DECERR; unfinished warm clear requires destination reset before re-admission"
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},
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{
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"name": "debug_hard_reset",
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"source": "jtag",
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"destination": "system",
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"primitive": "cdc_sync",
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"path": "rtl/ip/core/mgmt_debug_wrapper.sv",
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"instance": "u_dmihardreset_cdc_sync"
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},
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{
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"name": "i2s_configuration",
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"source": "peripheral",
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"destination": "audio",
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"primitive": "cdc_2phase",
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"path": "rtl/ip/serial/apb4_i2s.sv",
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"instance": "u_i2s_cfg_cdc"
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},
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{
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"name": "i2s_commands",
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"source": "peripheral",
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"destination": "audio",
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"primitive": "cdc_2phase",
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"path": "rtl/ip/serial/apb4_i2s.sv",
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"instance": "u_i2s_cmd_cdc"
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},
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{
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"name": "i2s_tx_samples",
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"source": "peripheral",
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"destination": "audio",
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"primitive": "cdc_fifo_warm_flush",
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"path": "rtl/ip/serial/apb4_i2s.sv",
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"instance": "u_tx_cdc_fifo"
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},
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{
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"name": "i2s_rx_samples",
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"source": "audio",
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"destination": "peripheral",
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"primitive": "cdc_fifo_warm_flush",
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"path": "rtl/ip/serial/apb4_i2s.sv",
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"instance": "u_rx_cdc_fifo"
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},
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{
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"name": "i2s_tx_occupancy",
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"source": "audio",
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"destination": "peripheral",
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"primitive": "cdc_2phase",
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"path": "rtl/ip/serial/apb4_i2s.sv",
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"instance": "u_tx_pop_cnt_cdc"
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},
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{
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"name": "i2s_rx_occupancy",
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"source": "audio",
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"destination": "peripheral",
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"primitive": "cdc_2phase",
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"path": "rtl/ip/serial/apb4_i2s.sv",
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"instance": "u_rx_push_cnt_cdc"
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},
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{
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"name": "dvp_configuration",
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"source": "peripheral",
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"destination": "dvp_pixel",
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"primitive": "cdc_2phase",
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"path": "rtl/ip/multimedia/axi4s_dvp.sv",
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"instance": "u_dvp_config_cdc"
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},
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{
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"name": "dvp_commands",
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"source": "peripheral",
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"destination": "dvp_pixel",
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"primitive": "cdc_2phase",
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"path": "rtl/ip/multimedia/axi4s_dvp.sv",
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"instance": "u_dvp_command_cdc"
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},
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{
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"name": "dvp_error_clear",
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"source": "peripheral",
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"destination": "dvp_pixel",
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"primitive": "cdc_2phase",
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"path": "rtl/ip/multimedia/axi4s_dvp.sv",
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"instance": "u_error_clear_cdc"
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},
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{
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"name": "dvp_status",
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"source": "dvp_pixel",
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"destination": "peripheral",
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"primitive": "cdc_2phase",
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"path": "rtl/ip/multimedia/axi4s_dvp.sv",
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"instance": "u_status_cdc"
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},
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{
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"name": "dvp_errors",
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"source": "dvp_pixel",
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"destination": "peripheral",
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"primitive": "cdc_2phase",
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"path": "rtl/ip/multimedia/axi4s_dvp.sv",
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"instance": "u_error_events_cdc"
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},
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{
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"name": "dvp_payload",
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"source": "dvp_pixel",
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"destination": "peripheral",
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"primitive": "cdc_fifo_warm_flush",
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"path": "rtl/ip/multimedia/axi4s_dvp.sv",
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"instance": "u_dvp_payload_fifo"
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},
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{
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"name": "dvp_statistics",
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"source": "dvp_pixel",
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"destination": "peripheral",
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"primitive": "cdc_2phase",
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"path": "rtl/ip/multimedia/axi4s_dvp.sv",
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"instance": "u_dvp_stats_cdc"
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},
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{
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"name": "dma_axi",
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"source": "peripheral",
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"destination": "system",
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"primitive": "tiny_axi4_async_bridge",
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"path": "rtl/tiny/top/retrosoc_tiny.sv",
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"instance": "u_dma_cdc",
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"source_reset": "s_dma_rst_n",
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"destination_reset": "s_fabric_rst_n",
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"reset_semantics": "five-edge link release; source-owned held responses survive destination reset; drain remaining W before B and synthesize only missing R beats with DECERR; unfinished warm clear requires destination reset before re-admission"
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},
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{
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"name": "rcu_commands",
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"source": "system",
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"destination": "aon",
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"primitive": "tiny_apb_async_bridge",
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"path": "rtl/tiny/top/tiny_sysctrl.sv",
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|
"instance": "u_rcu_cdc"
|
|
},
|
|
{
|
|
"name": "system_rate",
|
|
"source": "aon",
|
|
"destination": "system",
|
|
"primitive": "cdc_2phase",
|
|
"path": "rtl/tiny/top/retrosoc_tiny.sv",
|
|
"instance": "u_sys_rate_cdc"
|
|
},
|
|
{
|
|
"name": "peripheral_rate",
|
|
"source": "aon",
|
|
"destination": "peripheral",
|
|
"primitive": "cdc_2phase",
|
|
"path": "rtl/tiny/top/retrosoc_tiny.sv",
|
|
"instance": "u_pclk_rate_cdc"
|
|
},
|
|
{
|
|
"name": "dma_done",
|
|
"source": "peripheral",
|
|
"destination": "memory",
|
|
"primitive": "cdc_2phase",
|
|
"path": "rtl/tiny/top/retrosoc_tiny.sv",
|
|
"instance": "u_dma_done_cdc"
|
|
},
|
|
{
|
|
"name": "xpi_requests",
|
|
"source": "memory",
|
|
"destination": "peripheral",
|
|
"primitive": "cdc_sync",
|
|
"path": "rtl/tiny/top/retrosoc_tiny.sv",
|
|
"instance": "u_xpi_stall_sync"
|
|
}
|
|
],
|
|
"clock_contract": "TINY-R2-P7",
|
|
"macros": {
|
|
"ics55_pll": {
|
|
"cell": "PLL_TOP",
|
|
"scope": "single RCU-owned macro; off after cold reset; selectors 5/7",
|
|
"active_clock_domain": true,
|
|
"qualification": "digital activity/rate qualification only; no analog LOCK or characterized timing arcs"
|
|
}
|
|
},
|
|
"generated_apb_crossings": {
|
|
"generator": "scripts/generate_tiny.py",
|
|
"template": "tiny_apb_bridges.svh",
|
|
"primitive": "tiny_apb_async_bridge",
|
|
"source": "system",
|
|
"destinations": {
|
|
"aon": [
|
|
"clint",
|
|
"archinfo"
|
|
],
|
|
"memory": [
|
|
"xpi"
|
|
],
|
|
"peripheral": [
|
|
"gpio",
|
|
"uart0",
|
|
"timer0",
|
|
"timer1",
|
|
"i2c0",
|
|
"dma",
|
|
"pwm",
|
|
"rtc",
|
|
"wdg",
|
|
"rng",
|
|
"crc",
|
|
"ws2812",
|
|
"crypto",
|
|
"i2s",
|
|
"dvp",
|
|
"spi"
|
|
]
|
|
},
|
|
"same_clock_isolation": [
|
|
"sdio"
|
|
],
|
|
"native_system": [
|
|
"sysctrl",
|
|
"sram"
|
|
]
|
|
}
|
|
}
|