mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
31daf3e84c
Integrate the SPI-P2 shared-DMA ABI into the Tiny product: SPI0 at 0x1001D000 with IRQ25 and RCU target16, the four frozen Gen1 ALT routes, latched four-bit source qualification through the fabric and APB CDC, GPIO readiness/ownership guard, and the bounded rs_spi_* HAL with the TINY_SPI_P3_ACCEPTANCE ci_smoke image. Tiny DMA enables V2.2 requests 16/17 with exact fixed FIFO MMIO checks; Mini remains default-disabled and unchanged. Review closure: the DMA AXI4 master stages the origin channel with each burst so final and contended SPI alias bursts stay qualified, the RCU spare feedback bit is tied off for four-state simulators, and the clock-switch quiescence now includes the SPI session. Validation: full Pytest 2097 passed, 0 failed, 1 skipped (optional pypdf); both Tiny profiles pass the SPI-P3 Verilator acceptance (SIM_TEST_PASS cycles=1030088); R2-P7 Verilator acceptance, Mini DMA formal prove and cover, Mini/Tiny lint, Tiny Yosys synthesis, netsim-boot and OpenSTA pass; C format/policy/host tests and RTL format/style checks clean. Evidence and remaining obligations are recorded in docs/ip/spi-verification.md. Tiny Icarus behavioral remains blocked by the pre-existing observer/sv2v defect (routed to the R2 DV owners); Mini smoke synthesis host timeout is skipped per maintainer decision. Human phase acceptance and SPI-P4/P5 remain outstanding; phase_accepted stays false.
335 lines
12 KiB
Systemverilog
335 lines
12 KiB
Systemverilog
`timescale 1ns / 1ps
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module dma_origin_tb;
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localparam int NumChannels = 4;
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localparam logic [31:0] SourceBase = 32'h4000_0000;
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localparam logic [31:0] DestinationBase = 32'h5000_0000;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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logic [NumChannels*32-1:0] ch_cfg_i = '0;
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logic [NumChannels*32-1:0] src_addr_i = '0;
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logic [NumChannels*32-1:0] dst_addr_i = '0;
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logic [NumChannels*32-1:0] byte_count_i = '0;
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logic [NumChannels*32-1:0] request_sel_i = '0;
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logic [NumChannels*32-1:0] burst_cfg_i = '0;
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logic [NumChannels*32-1:0] tcd_head_i = '0;
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logic [NumChannels*32-1:0] tcd_count_i = '0;
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logic [NumChannels*32-1:0] crc_expected_i = '0;
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logic [ NumChannels-1:0] start_i = '0;
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logic [ NumChannels-1:0] suspend_i = '0;
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logic [ NumChannels-1:0] resume_i = '0;
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logic [ NumChannels-1:0] abort_i = '0;
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logic [ NumChannels-1:0] channel_reset_i = '0;
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logic [ NumChannels*3-1:0] event_clear_i = '0;
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logic [ NumChannels-1:0] busy_o;
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logic [ NumChannels-1:0] suspended_o;
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logic [ NumChannels-1:0] done_o;
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logic [ NumChannels-1:0] aborted_o;
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logic [ NumChannels-1:0] error_o;
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logic [ NumChannels-1:0] stream_last_o;
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logic [ NumChannels*3-1:0] event_status_o;
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logic [NumChannels*32-1:0] error_status_o;
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logic [NumChannels*32-1:0] error_addr_o;
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logic [NumChannels*32-1:0] current_src_o;
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logic [NumChannels*32-1:0] current_dst_o;
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logic [NumChannels*32-1:0] remaining_o;
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logic [NumChannels*32-1:0] bytes_done_o;
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logic [NumChannels*32-1:0] stall_cycles_lo_o;
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logic [NumChannels*32-1:0] stall_cycles_hi_o;
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logic [NumChannels*32-1:0] crc_result_o;
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logic first_error_valid_o;
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logic [ 1:0] first_error_channel_o;
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logic [ 8:0] first_error_status_o;
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logic [ 15:0] first_error_addr_hi_o;
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logic [ 15:0] request_status_o;
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logic xpi_xfer_done_o;
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integer ar_mismatch = 0;
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integer aw_mismatch = 0;
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integer w_mismatch = 0;
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integer ar_checked = 0;
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integer aw_checked = 0;
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integer w_checked = 0;
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logic [ 2:0] write_channel_q = '0;
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logic write_active_q = 1'b0;
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logic read_active_q = 1'b0;
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logic [ 4:0] read_beats_q = '0;
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logic [ 4:0] read_index_q = '0;
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logic [ 31:0] read_addr_q = '0;
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logic [ 4:0] write_beats_q = '0;
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logic [ 4:0] write_index_q = '0;
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logic write_response_q = 1'b0;
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dma_req_if req ();
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axi4_if #(
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.ADDR_WIDTH(32),
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.DATA_WIDTH(32),
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.ID_WIDTH (1),
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.USER_WIDTH(4)
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) axi4 (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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axi4_stream_if i2s_tx_axis (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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axi4_stream_if i2s_rx_axis (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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axi4_stream_if dvp_rx_axis (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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axi4_stream_if crypto_in_axis (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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axi4_stream_if crypto_out_axis (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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always #5 clk_i = ~clk_i;
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assign axi4.arready = !read_active_q;
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assign axi4.rvalid = read_active_q;
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assign axi4.rid = '0;
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assign axi4.rdata = 32'hA500_0000 + ((read_addr_q - SourceBase) >> 2) + read_index_q;
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assign axi4.rresp = `AXI4_RESP_OKAY;
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assign axi4.rlast = (read_index_q + 1'b1) == read_beats_q;
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assign axi4.ruser = '0;
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assign axi4.awready = !write_active_q && !write_response_q;
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assign axi4.wready = write_active_q;
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assign axi4.bid = '0;
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assign axi4.bresp = `AXI4_RESP_OKAY;
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assign axi4.buser = '0;
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assign axi4.bvalid = write_response_q;
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assign i2s_tx_axis.tready = 1'b0;
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assign i2s_rx_axis.tdata = '0;
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assign i2s_rx_axis.tkeep = '0;
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assign i2s_rx_axis.tstrb = '0;
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assign i2s_rx_axis.tlast = 1'b0;
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assign i2s_rx_axis.tid = '0;
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assign i2s_rx_axis.tdest = '0;
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assign i2s_rx_axis.tuser = '0;
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assign i2s_rx_axis.tvalid = 1'b0;
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assign dvp_rx_axis.tdata = '0;
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assign dvp_rx_axis.tkeep = '0;
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assign dvp_rx_axis.tstrb = '0;
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assign dvp_rx_axis.tlast = 1'b0;
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assign dvp_rx_axis.tid = '0;
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assign dvp_rx_axis.tdest = '0;
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assign dvp_rx_axis.tuser = '0;
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assign dvp_rx_axis.tvalid = 1'b0;
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assign crypto_in_axis.tready = 1'b0;
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assign crypto_out_axis.tdata = '0;
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assign crypto_out_axis.tkeep = '0;
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assign crypto_out_axis.tstrb = '0;
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assign crypto_out_axis.tlast = 1'b0;
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assign crypto_out_axis.tid = '0;
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assign crypto_out_axis.tdest = '0;
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assign crypto_out_axis.tuser = '0;
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assign crypto_out_axis.tvalid = 1'b0;
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always_ff @(posedge clk_i or negedge rst_n_i) begin
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if (!rst_n_i) begin
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read_active_q <= 1'b0;
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read_addr_q <= '0;
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read_beats_q <= '0;
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read_index_q <= '0;
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write_active_q <= 1'b0;
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write_channel_q <= '0;
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write_beats_q <= '0;
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write_index_q <= '0;
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write_response_q <= 1'b0;
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end else begin
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if (axi4.arvalid && axi4.arready) begin
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read_active_q <= 1'b1;
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read_addr_q <= axi4.araddr;
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read_beats_q <= {1'b0, axi4.arlen} + 5'd1;
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read_index_q <= '0;
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end else if (axi4.rvalid && axi4.rready && axi4.rlast) begin
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read_active_q <= 1'b0;
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end else if (axi4.rvalid && axi4.rready) begin
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read_index_q <= read_index_q + 5'd1;
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end
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if (axi4.awvalid && axi4.awready) begin
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write_active_q <= 1'b1;
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write_channel_q <= axi4.awuser[2:0];
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write_beats_q <= {1'b0, axi4.awlen} + 5'd1;
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write_index_q <= '0;
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write_response_q <= 1'b0;
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end else if (axi4.wvalid && axi4.wready && axi4.wlast) begin
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write_active_q <= 1'b0;
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write_response_q <= 1'b1;
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end else if (axi4.wvalid && axi4.wready) begin
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write_index_q <= write_index_q + 5'd1;
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end else if (axi4.bvalid && axi4.bready) begin
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write_response_q <= 1'b0;
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end
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end
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end
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always_ff @(posedge clk_i) begin
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if (rst_n_i) begin
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if (axi4.arvalid && axi4.arready) begin
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ar_checked <= ar_checked + 1;
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if (axi4.aruser !== {1'b1, 3'((axi4.araddr - SourceBase) >> 12)}) begin
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ar_mismatch <= ar_mismatch + 1;
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end
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end
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if (axi4.awvalid && axi4.awready) begin
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aw_checked <= aw_checked + 1;
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if (axi4.awuser !== {1'b1, 3'((axi4.awaddr - DestinationBase) >> 12)}) begin
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aw_mismatch <= aw_mismatch + 1;
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end
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end
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if (axi4.wvalid && axi4.wready) begin
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w_checked <= w_checked + 1;
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if (axi4.wuser !== {1'b1, write_channel_q}) begin
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w_mismatch <= w_mismatch + 1;
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end
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end
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end
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end
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dma_core #(
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.NumChannels (NumChannels),
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.MaxBurstBeats (16),
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.FifoDepth (16),
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.EnableOriginQualifier(1'b1)
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) u_dma_core (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.global_reset_i (1'b0),
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.global_error_clear_i (1'b0),
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.ch_cfg_i (ch_cfg_i),
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.tcd_head_i (tcd_head_i),
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.tcd_count_i (tcd_count_i),
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.crc_expected_i (crc_expected_i),
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.src_addr_i (src_addr_i),
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.dst_addr_i (dst_addr_i),
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.byte_count_i (byte_count_i),
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.request_sel_i (request_sel_i),
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.burst_cfg_i (burst_cfg_i),
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.start_i (start_i),
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.suspend_i (suspend_i),
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.resume_i (resume_i),
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.abort_i (abort_i),
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.channel_reset_i (channel_reset_i),
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.event_clear_i (event_clear_i),
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.busy_o (busy_o),
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.suspended_o (suspended_o),
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.done_o (done_o),
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.aborted_o (aborted_o),
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.error_o (error_o),
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.stream_last_o (stream_last_o),
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.event_status_o (event_status_o),
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.error_status_o (error_status_o),
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.error_addr_o (error_addr_o),
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.current_src_o (current_src_o),
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.current_dst_o (current_dst_o),
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.remaining_o (remaining_o),
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.bytes_done_o (bytes_done_o),
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.stall_cycles_lo_o (stall_cycles_lo_o),
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.stall_cycles_hi_o (stall_cycles_hi_o),
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.crc_result_o (crc_result_o),
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.first_error_valid_o (first_error_valid_o),
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.first_error_channel_o(first_error_channel_o),
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.first_error_status_o (first_error_status_o),
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.first_error_addr_hi_o(first_error_addr_hi_o),
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.request_status_o (request_status_o),
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.xpi_xfer_done_o (xpi_xfer_done_o),
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.req (req),
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.axi4 (axi4),
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.i2s_tx_axis (i2s_tx_axis),
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.i2s_rx_axis (i2s_rx_axis),
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.dvp_rx_axis (dvp_rx_axis),
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.crypto_in_axis (crypto_in_axis),
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.crypto_out_axis (crypto_out_axis)
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);
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task automatic configure_channel(input integer channel, input logic [31:0] byte_count);
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begin
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ch_cfg_i[(channel*32)+:32] = {22'd0, 2'd1, 1'b1, 1'b1, 2'd2, 1'b0, 3'd0};
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src_addr_i[(channel*32)+:32] = SourceBase + (32'(channel) << 12);
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dst_addr_i[(channel*32)+:32] = DestinationBase + (32'(channel) << 12);
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byte_count_i[(channel*32)+:32] = byte_count;
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request_sel_i[(channel*32)+:32] = 32'd0;
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burst_cfg_i[(channel*32)+:32] = {27'd0, 5'd1};
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end
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endtask
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task automatic wait_done(input integer channel);
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integer timeout;
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begin
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timeout = 0;
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while (!done_o[channel] && !error_o[channel] && (timeout < 100000)) begin
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@(posedge clk_i);
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timeout = timeout + 1;
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end
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if (timeout >= 100000) $fatal(1, "channel %0d never completed", channel);
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end
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endtask
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initial begin
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req.i2s_tx_proc = 1'b1;
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req.i2s_rx_proc = 1'b1;
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req.qspi_tx_proc = 1'b1;
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req.qspi_rx_proc = 1'b1;
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req.uart_tx_proc = 1'b1;
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req.uart_rx_proc = 1'b1;
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req.i2c0_tx_proc = 1'b1;
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req.i2c0_rx_proc = 1'b1;
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req.i2c1_tx_proc = 1'b1;
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req.i2c1_rx_proc = 1'b1;
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req.crypto_in_proc = 1'b1;
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req.crypto_out_proc = 1'b1;
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repeat (3) @(posedge clk_i);
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rst_n_i = 1'b1;
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repeat (4) @(posedge clk_i);
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// Idle arbiter: one single-beat job on nonzero channel 2.
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configure_channel(2, 32'd4);
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@(negedge clk_i);
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start_i[2] = 1'b1;
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@(negedge clk_i);
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start_i[2] = 1'b0;
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wait_done(2);
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// Contended arbiter: three channels rotate single-beat bursts.
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configure_channel(1, 32'd64);
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configure_channel(2, 32'd64);
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configure_channel(3, 32'd64);
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@(negedge clk_i);
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start_i[1] = 1'b1;
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start_i[2] = 1'b1;
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start_i[3] = 1'b1;
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@(negedge clk_i);
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start_i = '0;
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wait_done(1);
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wait_done(2);
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wait_done(3);
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if ((ar_checked == 0) || (aw_checked == 0) || (w_checked == 0)) begin
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$fatal(1, "origin checks never ran");
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end
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if ((ar_mismatch != 0) || (aw_mismatch != 0) || (w_mismatch != 0) || (error_o != '0)) begin
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$fatal(1, "origin mismatch ar=%0d aw=%0d w=%0d", ar_mismatch, aw_mismatch, w_mismatch);
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end
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$display("DMA origin qualifier staging test passed ar=%0d aw=%0d w=%0d", ar_checked,
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aw_checked, w_checked);
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$finish;
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end
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initial begin
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repeat (1000000) @(posedge clk_i);
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$fatal(1, "SIM_TEST_TIMEOUT DMA origin");
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end
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endmodule
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