mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
39bc1c84b4
- Implemented tests for the deterministic baseline JPEG reference model in , covering encoding, decoding, quality scaling, and error handling. - Created to ensure synchronization between RTL and C register constants for JPEG. - Updated to reflect changes in the number of APB interfaces and IRQ mappings, ensuring the topology generates correct bindings.
92 lines
2.6 KiB
Systemverilog
92 lines
2.6 KiB
Systemverilog
`timescale 1ns / 1ps
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module jpeg_byte_joiner_tb;
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logic clk = 1'b0;
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logic rst_n = 1'b0;
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logic [63:0] input_data;
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logic [ 7:0] input_keep;
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logic input_valid;
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logic input_ready;
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logic input_last;
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logic error_flag;
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int output_beats;
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axi4_stream_if #(
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.DATA_WIDTH(64)
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) output_axis (
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.aclk (clk),
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.aresetn(rst_n)
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);
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always #5 clk = ~clk;
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jpeg_byte_joiner u_dut (
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.clk_i (clk),
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.rst_n_i (rst_n),
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.input_data_i (input_data),
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.input_keep_i (input_keep),
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.input_valid_i(input_valid),
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.input_ready_o(input_ready),
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.input_last_i (input_last),
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.output_axis (output_axis),
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.error_o (error_flag)
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);
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task automatic send_beat(input logic [63:0] data_i, input logic [7:0] keep_i, input logic last_i);
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begin
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@(negedge clk);
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input_data = data_i;
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input_keep = keep_i;
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input_last = last_i;
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input_valid = 1'b1;
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@(posedge clk);
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while (!input_ready) @(posedge clk);
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@(negedge clk);
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input_valid = 1'b0;
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end
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endtask
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always @(posedge clk) begin
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if (rst_n && output_axis.tvalid && output_axis.tready) begin
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if (output_beats == 0) begin
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if (output_axis.tdata != 64'ha2a1a00504030201 || output_axis.tkeep != 8'hff ||
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output_axis.tlast) begin
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$fatal(1, "joined full beat mismatch");
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end
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end else if (output_beats == 1) begin
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if (output_axis.tdata[15:0] != 16'hd9ff || output_axis.tkeep != 8'h03 ||
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!output_axis.tlast) begin
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$fatal(1, "joined final beat mismatch");
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end
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end else begin
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$fatal(1, "unexpected joined output beat");
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end
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output_beats <= output_beats + 1;
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end
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end
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initial begin
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input_data = '0;
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input_keep = '0;
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input_valid = 1'b0;
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input_last = 1'b0;
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output_axis.tready = 1'b0;
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output_beats = 0;
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repeat (3) @(posedge clk);
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rst_n = 1'b1;
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send_beat(64'h0000000504030201, 8'h1f, 1'b0);
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send_beat(64'h0000000000a2a1a0, 8'h07, 1'b0);
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repeat (2) @(negedge clk);
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if (!output_axis.tvalid || output_axis.tdata != 64'ha2a1a00504030201) begin
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$fatal(1, "full output was not held under backpressure: valid=%0d data=%h keep=%h",
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output_axis.tvalid, output_axis.tdata, output_axis.tkeep);
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end
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output_axis.tready = 1'b1;
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send_beat(64'h000000000000d9ff, 8'h03, 1'b1);
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while (output_beats < 2) @(negedge clk);
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if (error_flag) $fatal(1, "unexpected byte joiner error");
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$display("JPEG byte joiner tests passed");
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$finish;
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end
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endmodule
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