mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
3aa3d937e1
- Updated filelist to include new timer peripheral files. - Enhanced formal file generation script to support timer target. - Created timer formal design and properties for formal verification. - Modified formal makefile to include timer targets and source files. - Added timer-related source files to software makefile. - Updated core and management wrappers to include debug halted signal. - Implemented timer testbench for RTL simulation. - Added regression tests for timer functionality in Python. - Introduced timer helper functions in C tests for validation.
293 lines
22 KiB
C
293 lines
22 KiB
C
#ifndef _RETROSOC_DEF_H_
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#define _RETROSOC_DEF_H_
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#include <stdint.h>
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#include <stdbool.h>
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#include <retrosoc/generated/memory_map.h>
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#include <retrosoc/generated/user_extensions.h>
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#define HW_CORE "Management Hazard3"
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#define CPU_FREQ 72 // unit: MHz
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#define UART_BPS 921600 // unit: bps
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#define PSRAM_NUM 4
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#define PSRAM_SCLK_MIN_FREQ 12 // unit: MHz
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#define PSRAM_SCLK_MAX_FREQ 133 // unit: MHz
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#define PSRAM_SCLK_FREQ (CPU_FREQ / 2)
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#define SPFS_MEM_START RS_SOC_FLASH_BASE
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#define SPFS_MEM_OFFST RS_SOC_FLASH_SIZE
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#define SRAM_MEM_START RS_SOC_SRAM_BASE
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#define SRAM_MEM_OFFST RS_SOC_SRAM_SIZE
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#define SDRAM_MEM_START RS_SOC_SDRAM_BASE
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#define SDRAM_MEM_OFFST RS_SOC_SDRAM_SIZE
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#define PSRAM_MEM_START RS_SOC_PSRAM_BASE
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#define PSRAM_MEM_OFFST RS_SOC_PSRAM_SIZE
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#define XPI_MEM_START RS_SOC_XPI_BASE
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#define XPI_MEM_OFFST RS_SOC_XPI_SIZE
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#define TF_CARD_START RS_SOC_SPISD_BASE
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#define TF_CARD_OFFST RS_SOC_SPISD_SIZE
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#define RS_SOC_REG32(base, offset) (*(volatile uint32_t *)(uintptr_t)((base) + (offset)))
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// gpio
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#define reg_gpio_oe RS_SOC_REG32(RS_SOC_RIBP_GPIO_BASE, UINT32_C(0x00))
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#define reg_gpio_cs RS_SOC_REG32(RS_SOC_RIBP_GPIO_BASE, UINT32_C(0x04))
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#define reg_gpio_pu RS_SOC_REG32(RS_SOC_RIBP_GPIO_BASE, UINT32_C(0x08))
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#define reg_gpio_pd RS_SOC_REG32(RS_SOC_RIBP_GPIO_BASE, UINT32_C(0x0C))
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#define reg_gpio_do RS_SOC_REG32(RS_SOC_RIBP_GPIO_BASE, UINT32_C(0x10))
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#define reg_gpio_di RS_SOC_REG32(RS_SOC_RIBP_GPIO_BASE, UINT32_C(0x14))
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#define reg_gpio_ien RS_SOC_REG32(RS_SOC_RIBP_GPIO_BASE, UINT32_C(0x18))
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#define reg_gpio_itype0 RS_SOC_REG32(RS_SOC_RIBP_GPIO_BASE, UINT32_C(0x1C))
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#define reg_gpio_itype1 RS_SOC_REG32(RS_SOC_RIBP_GPIO_BASE, UINT32_C(0x20))
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#define reg_gpio_istat RS_SOC_REG32(RS_SOC_RIBP_GPIO_BASE, UINT32_C(0x24))
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#define reg_gpio_iofcfg RS_SOC_REG32(RS_SOC_RIBP_GPIO_BASE, UINT32_C(0x28))
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#define reg_gpio_pinmux RS_SOC_REG32(RS_SOC_RIBP_GPIO_BASE, UINT32_C(0x2C))
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#define reg_gpio_user_sel RS_SOC_REG32(RS_SOC_RIBP_GPIO_BASE, UINT32_C(0x30))
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#define reg_gpio_user_lock RS_SOC_REG32(RS_SOC_RIBP_GPIO_BASE, UINT32_C(0x34))
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#define reg_gpio_user_status RS_SOC_REG32(RS_SOC_RIBP_GPIO_BASE, UINT32_C(0x38))
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// uart0
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#define reg_uart0_clkdiv RS_SOC_REG32(RS_SOC_RIBP_UART0_BASE, UINT32_C(0x00))
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#define reg_uart0_data RS_SOC_REG32(RS_SOC_RIBP_UART0_BASE, UINT32_C(0x04))
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// psram
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#define reg_psram_wait RS_SOC_REG32(RS_SOC_RIBP_PSRAM_BASE, UINT32_C(0x00))
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#define reg_psram_chd RS_SOC_REG32(RS_SOC_RIBP_PSRAM_BASE, UINT32_C(0x04))
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#define reg_psram_init RS_SOC_REG32(RS_SOC_RIBP_PSRAM_BASE, UINT32_C(0x08))
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// spisd
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#define reg_spisd_mode RS_SOC_REG32(RS_SOC_RIBP_SPISD_BASE, UINT32_C(0x00))
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#define reg_spisd_clkdiv RS_SOC_REG32(RS_SOC_RIBP_SPISD_BASE, UINT32_C(0x04))
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#define reg_spisd_addr RS_SOC_REG32(RS_SOC_RIBP_SPISD_BASE, UINT32_C(0x08))
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#define reg_spisd_txdata RS_SOC_REG32(RS_SOC_RIBP_SPISD_BASE, UINT32_C(0x0C))
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#define reg_spisd_rxdata RS_SOC_REG32(RS_SOC_RIBP_SPISD_BASE, UINT32_C(0x10))
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#define reg_spisd_status RS_SOC_REG32(RS_SOC_RIBP_SPISD_BASE, UINT32_C(0x14))
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#define reg_spisd_sync RS_SOC_REG32(RS_SOC_RIBP_SPISD_BASE, UINT32_C(0x18))
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// i2c0
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#define reg_i2c0_clkdiv RS_SOC_REG32(RS_SOC_RIBP_I2C0_BASE, UINT32_C(0x00))
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#define reg_i2c0_devaddr RS_SOC_REG32(RS_SOC_RIBP_I2C0_BASE, UINT32_C(0x04))
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#define reg_i2c0_regaddr RS_SOC_REG32(RS_SOC_RIBP_I2C0_BASE, UINT32_C(0x08))
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#define reg_i2c0_txdata RS_SOC_REG32(RS_SOC_RIBP_I2C0_BASE, UINT32_C(0x0C))
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#define reg_i2c0_rxdata RS_SOC_REG32(RS_SOC_RIBP_I2C0_BASE, UINT32_C(0x10))
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#define reg_i2c0_xfer RS_SOC_REG32(RS_SOC_RIBP_I2C0_BASE, UINT32_C(0x14))
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#define reg_i2c0_cfg RS_SOC_REG32(RS_SOC_RIBP_I2C0_BASE, UINT32_C(0x18))
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#define reg_i2c0_status RS_SOC_REG32(RS_SOC_RIBP_I2C0_BASE, UINT32_C(0x1C))
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// i2s
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#define reg_i2s_mode RS_SOC_REG32(RS_SOC_RIBP_I2S_BASE, UINT32_C(0x00))
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#define reg_i2s_format RS_SOC_REG32(RS_SOC_RIBP_I2S_BASE, UINT32_C(0x04))
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#define reg_i2s_upbound RS_SOC_REG32(RS_SOC_RIBP_I2S_BASE, UINT32_C(0x08))
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#define reg_i2s_lowbound RS_SOC_REG32(RS_SOC_RIBP_I2S_BASE, UINT32_C(0x0C))
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#define reg_i2s_recven RS_SOC_REG32(RS_SOC_RIBP_I2S_BASE, UINT32_C(0x10))
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#define reg_i2s_txdata RS_SOC_REG32(RS_SOC_RIBP_I2S_BASE, UINT32_C(0x14))
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#define reg_i2s_rxdata RS_SOC_REG32(RS_SOC_RIBP_I2S_BASE, UINT32_C(0x18))
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#define reg_i2s_status RS_SOC_REG32(RS_SOC_RIBP_I2S_BASE, UINT32_C(0x1C))
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// ws2812
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#define reg_ws2812_bit_cycles RS_SOC_REG32(RS_SOC_RIBP_WS2812_BASE, UINT32_C(0x00))
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#define reg_ws2812_t0h_cycles RS_SOC_REG32(RS_SOC_RIBP_WS2812_BASE, UINT32_C(0x04))
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#define reg_ws2812_t1h_cycles RS_SOC_REG32(RS_SOC_RIBP_WS2812_BASE, UINT32_C(0x08))
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#define reg_ws2812_reset_cycles RS_SOC_REG32(RS_SOC_RIBP_WS2812_BASE, UINT32_C(0x0C))
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#define reg_ws2812_txdata RS_SOC_REG32(RS_SOC_RIBP_WS2812_BASE, UINT32_C(0x10))
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#define reg_ws2812_ctrl RS_SOC_REG32(RS_SOC_RIBP_WS2812_BASE, UINT32_C(0x14))
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#define reg_ws2812_status RS_SOC_REG32(RS_SOC_RIBP_WS2812_BASE, UINT32_C(0x18))
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#define reg_ws2812_frame_words RS_SOC_REG32(RS_SOC_RIBP_WS2812_BASE, UINT32_C(0x1C))
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#define reg_ws2812_fifo_level RS_SOC_REG32(RS_SOC_RIBP_WS2812_BASE, UINT32_C(0x20))
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#define reg_ws2812_fifo_watermark RS_SOC_REG32(RS_SOC_RIBP_WS2812_BASE, UINT32_C(0x24))
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#define reg_ws2812_remaining_words RS_SOC_REG32(RS_SOC_RIBP_WS2812_BASE, UINT32_C(0x28))
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#define reg_ws2812_error_status RS_SOC_REG32(RS_SOC_RIBP_WS2812_BASE, UINT32_C(0x2C))
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#define reg_ws2812_intr_state RS_SOC_REG32(RS_SOC_RIBP_WS2812_BASE, UINT32_C(0x30))
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#define reg_ws2812_intr_enable RS_SOC_REG32(RS_SOC_RIBP_WS2812_BASE, UINT32_C(0x34))
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#define reg_ws2812_intr_test RS_SOC_REG32(RS_SOC_RIBP_WS2812_BASE, UINT32_C(0x38))
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#define reg_ws2812_ip_info RS_SOC_REG32(RS_SOC_RIBP_WS2812_BASE, UINT32_C(0x3C))
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// xpi
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#define reg_xpi_cfgidx RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x00))
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#define reg_xpi_accmd RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x04))
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#define reg_xpi_mmstad RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x08))
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#define reg_xpi_mmoffst RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x0C))
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#define reg_xpi_mode RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x10))
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#define reg_xpi_nss RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x14))
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#define reg_xpi_clkdiv RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x18))
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#define reg_xpi_rdwr RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x1C))
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#define reg_xpi_revdat RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x20))
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#define reg_xpi_txupb RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x24))
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#define reg_xpi_txlowb RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x28))
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#define reg_xpi_rxupb RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x2C))
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#define reg_xpi_rxlowb RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x30))
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#define reg_xpi_flush RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x34))
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#define reg_xpi_cmdtyp RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x38))
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#define reg_xpi_cmdlen RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x3C))
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#define reg_xpi_cmddat RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x40))
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#define reg_xpi_adrtyp RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x44))
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#define reg_xpi_adrlen RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x48))
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#define reg_xpi_adrdat RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x4C))
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#define reg_xpi_alttyp RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x50))
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#define reg_xpi_altlen RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x54))
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#define reg_xpi_altdat RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x58))
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#define reg_xpi_tdulen RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x5C))
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#define reg_xpi_rdulen RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x60))
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#define reg_xpi_dattyp RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x64))
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#define reg_xpi_datlen RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x68))
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#define reg_xpi_datbit RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x6C))
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#define reg_xpi_hlvlen RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x70))
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#define reg_xpi_txdata RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x74))
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#define reg_xpi_rxdata RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x78))
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#define reg_xpi_start RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x7C))
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#define reg_xpi_status RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x80))
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// dma(32b xfer, hardware trigger by I2S fifo, QSPI fifo)
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#define reg_dma_mode RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x00))
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#define reg_dma_srcaddr RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x04))
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#define reg_dma_srcincr RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x08))
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#define reg_dma_dstaddr RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x0C))
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#define reg_dma_dstincr RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x10))
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#define reg_dma_xferlen RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x14))
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#define reg_dma_start RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x18))
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#define reg_dma_stop RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x1C))
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#define reg_dma_reset RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x20))
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#define reg_dma_status RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x24))
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#define reg_dma_fsm RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x28))
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#define reg_dma_error_status RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x2C))
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#define reg_dma_error_addr RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x30))
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#define RS_SOC_DMA_ERROR_PENDING UINT32_C(0x00000001)
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#define RS_SOC_DMA_ERROR_RESPONSE_SHIFT 1U
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#define RS_SOC_DMA_ERROR_RESPONSE_MASK UINT32_C(0x0000000E)
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// sys ctrl
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#define RS_SOC_SYSCTRL_REG32(offset) RS_SOC_REG32(RS_SOC_RIBP_SYSCTRL_BASE, (offset))
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#define reg_sysctrl_coresel RS_SOC_REG32(RS_SOC_RIBP_SYSCTRL_BASE, UINT32_C(0x00))
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#define reg_sysctrl_ipsel RS_SOC_REG32(RS_SOC_RIBP_SYSCTRL_BASE, UINT32_C(0x04))
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#define reg_sysctrl_pll_cfg RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PLL_CFG_OFFSET)
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#define reg_sysctrl_pll_cmd RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PLL_CMD_OFFSET)
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/* Status: bit 0 pending (W1C), bit 1 write, bits 3:2 reason (1 unmapped, 2 reserved). */
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#define reg_sysctrl_bus_fault_status RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_FAULT_STATUS_OFFSET)
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#define reg_sysctrl_bus_fault_addr RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_FAULT_ADDR_OFFSET)
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#define reg_sysctrl_bus_fault_count RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_FAULT_COUNT_OFFSET)
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#define reg_sysctrl_pll_status RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PLL_STATUS_OFFSET)
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#define reg_sysctrl_user_core_reset RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_USER_CORE_RESET_OFFSET)
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#define reg_sysctrl_user_core_status RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_USER_CORE_STATUS_OFFSET)
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#define reg_sysctrl_bus_fault_master RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_FAULT_MASTER_OFFSET)
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#define reg_sysctrl_bus_fault_detail RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_FAULT_DETAIL_OFFSET)
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#define reg_sysctrl_perf_ctrl RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_CTRL_OFFSET)
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#define reg_sysctrl_perf_mgmt_wait_lo RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_MGMT_WAIT_LO_OFFSET)
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#define reg_sysctrl_perf_mgmt_wait_hi RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_MGMT_WAIT_HI_OFFSET)
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#define reg_sysctrl_perf_user_wait_lo RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_USER_WAIT_LO_OFFSET)
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#define reg_sysctrl_perf_user_wait_hi RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_USER_WAIT_HI_OFFSET)
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#define reg_sysctrl_perf_dma_wait_lo RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_DMA_WAIT_LO_OFFSET)
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#define reg_sysctrl_perf_dma_wait_hi RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_DMA_WAIT_HI_OFFSET)
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#define reg_sysctrl_perf_ribp_wait_lo RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_RIBP_WAIT_LO_OFFSET)
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#define reg_sysctrl_perf_ribp_wait_hi RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_RIBP_WAIT_HI_OFFSET)
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#define reg_sysctrl_perf_apb_wait_lo RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_APB_WAIT_LO_OFFSET)
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#define reg_sysctrl_perf_apb_wait_hi RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_APB_WAIT_HI_OFFSET)
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#define reg_sysctrl_perf_sdram_wait_lo \
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RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_SDRAM_WAIT_LO_OFFSET)
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#define reg_sysctrl_perf_sdram_wait_hi \
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RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_SDRAM_WAIT_HI_OFFSET)
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#define reg_sysctrl_perf_psram_wait_lo \
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RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_PSRAM_WAIT_LO_OFFSET)
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#define reg_sysctrl_perf_psram_wait_hi \
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RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_PSRAM_WAIT_HI_OFFSET)
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#define reg_sysctrl_perf_flash_wait_lo \
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RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_FLASH_WAIT_LO_OFFSET)
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#define reg_sysctrl_perf_flash_wait_hi \
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RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_FLASH_WAIT_HI_OFFSET)
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#define reg_sysctrl_test_status RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_TEST_STATUS_OFFSET)
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#define RS_SOC_TEST_STATUS_VALID UINT32_C(0x80000000)
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#define RS_SOC_TEST_STATUS_CODE_SHIFT 8U
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#define RS_SOC_TEST_STATUS_PASS UINT32_C(0x00000001)
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#define RS_SOC_BUS_FAULT_PENDING UINT32_C(0x00000001)
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#define RS_SOC_BUS_FAULT_WRITE UINT32_C(0x00000002)
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#define RS_SOC_BUS_FAULT_REASON_MASK UINT32_C(0x0000000C)
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#define RS_SOC_BUS_FAULT_REASON_UNMAPPED UINT32_C(0x00000004)
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#define RS_SOC_BUS_FAULT_REASON_RESERVED UINT32_C(0x00000008)
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#define RS_SOC_BUS_FAULT_RESPONSE_OK UINT32_C(0x00000000)
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#define RS_SOC_BUS_FAULT_RESPONSE_DECERR UINT32_C(0x00000001)
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#define RS_SOC_BUS_FAULT_RESPONSE_PROTERR UINT32_C(0x00000002)
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#define RS_SOC_BUS_FAULT_RESPONSE_SLVERR UINT32_C(0x00000003)
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#define RS_SOC_BUS_FAULT_RESPONSE_TIMEOUT UINT32_C(0x00000004)
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#define RS_SOC_BUS_FAULT_RESPONSE_RESERVED UINT32_C(0x00000005)
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#define RS_SOC_PERF_CTRL_ENABLE UINT32_C(0x00000001)
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#define RS_SOC_PERF_CTRL_CLEAR UINT32_C(0x00000002)
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#define RS_SOC_PERF_CTRL_SNAPSHOT UINT32_C(0x00000004)
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// clint
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#define reg_clint_mtimel RS_SOC_REG32(RS_SOC_RIBP_CLINT_BASE, UINT32_C(0x00))
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#define reg_clint_mtimeh RS_SOC_REG32(RS_SOC_RIBP_CLINT_BASE, UINT32_C(0x04))
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#define reg_clint_mtimecmpl RS_SOC_REG32(RS_SOC_RIBP_CLINT_BASE, UINT32_C(0x08))
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#define reg_clint_mtimecmph RS_SOC_REG32(RS_SOC_RIBP_CLINT_BASE, UINT32_C(0x0C))
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#define reg_clint_msip RS_SOC_REG32(RS_SOC_RIBP_CLINT_BASE, UINT32_C(0x10))
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#define reg_clint_clkdiv RS_SOC_REG32(RS_SOC_RIBP_CLINT_BASE, UINT32_C(0x14))
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// sdram
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#define reg_sdram_clkdiv RS_SOC_REG32(RS_SOC_RIBP_SDRAM_BASE, UINT32_C(0x00))
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#define reg_sdram_cfg RS_SOC_REG32(RS_SOC_RIBP_SDRAM_BASE, UINT32_C(0x04))
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// dvp
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#define reg_dvp_recven RS_SOC_REG32(RS_SOC_RIBP_DVP_BASE, UINT32_C(0x00))
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#define reg_dvp_rxdata RS_SOC_REG32(RS_SOC_RIBP_DVP_BASE, UINT32_C(0x04))
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#define reg_dvp_status RS_SOC_REG32(RS_SOC_RIBP_DVP_BASE, UINT32_C(0x08))
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// i2c1
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#define reg_i2c1_clkdiv RS_SOC_REG32(RS_SOC_RIBP_I2C1_BASE, UINT32_C(0x00))
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#define reg_i2c1_devaddr RS_SOC_REG32(RS_SOC_RIBP_I2C1_BASE, UINT32_C(0x04))
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#define reg_i2c1_regaddr RS_SOC_REG32(RS_SOC_RIBP_I2C1_BASE, UINT32_C(0x08))
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#define reg_i2c1_txdata RS_SOC_REG32(RS_SOC_RIBP_I2C1_BASE, UINT32_C(0x0C))
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#define reg_i2c1_rxdata RS_SOC_REG32(RS_SOC_RIBP_I2C1_BASE, UINT32_C(0x10))
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#define reg_i2c1_xfer RS_SOC_REG32(RS_SOC_RIBP_I2C1_BASE, UINT32_C(0x14))
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#define reg_i2c1_cfg RS_SOC_REG32(RS_SOC_RIBP_I2C1_BASE, UINT32_C(0x18))
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#define reg_i2c1_status RS_SOC_REG32(RS_SOC_RIBP_I2C1_BASE, UINT32_C(0x1C))
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// archinfo
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#define reg_archinfo_sys RS_SOC_REG32(RS_SOC_APB_ARCHINFO_BASE, UINT32_C(0x00))
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#define reg_archinfo_idl RS_SOC_REG32(RS_SOC_APB_ARCHINFO_BASE, UINT32_C(0x04))
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#define reg_archinfo_idh RS_SOC_REG32(RS_SOC_APB_ARCHINFO_BASE, UINT32_C(0x08))
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// rng
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#define reg_rng_ctrl RS_SOC_REG32(RS_SOC_APB_RNG_BASE, UINT32_C(0x00))
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#define reg_rng_seed RS_SOC_REG32(RS_SOC_APB_RNG_BASE, UINT32_C(0x04))
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#define reg_rng_val RS_SOC_REG32(RS_SOC_APB_RNG_BASE, UINT32_C(0x08))
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// uart
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#define reg_uart1_lcr RS_SOC_REG32(RS_SOC_APB_UART1_BASE, UINT32_C(0x00))
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#define reg_uart1_div RS_SOC_REG32(RS_SOC_APB_UART1_BASE, UINT32_C(0x04))
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#define reg_uart1_trx RS_SOC_REG32(RS_SOC_APB_UART1_BASE, UINT32_C(0x08))
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#define reg_uart1_fcr RS_SOC_REG32(RS_SOC_APB_UART1_BASE, UINT32_C(0x0C))
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#define reg_uart1_lsr RS_SOC_REG32(RS_SOC_APB_UART1_BASE, UINT32_C(0x10))
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// pwm
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#define reg_pwm_ctrl RS_SOC_REG32(RS_SOC_APB_PWM_BASE, UINT32_C(0x00))
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#define reg_pwm_pscr RS_SOC_REG32(RS_SOC_APB_PWM_BASE, UINT32_C(0x04))
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#define reg_pwm_cnt RS_SOC_REG32(RS_SOC_APB_PWM_BASE, UINT32_C(0x08))
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#define reg_pwm_cmp RS_SOC_REG32(RS_SOC_APB_PWM_BASE, UINT32_C(0x0C))
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#define reg_pwm_cr0 RS_SOC_REG32(RS_SOC_APB_PWM_BASE, UINT32_C(0x10))
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#define reg_pwm_cr1 RS_SOC_REG32(RS_SOC_APB_PWM_BASE, UINT32_C(0x14))
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#define reg_pwm_cr2 RS_SOC_REG32(RS_SOC_APB_PWM_BASE, UINT32_C(0x18))
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#define reg_pwm_cr3 RS_SOC_REG32(RS_SOC_APB_PWM_BASE, UINT32_C(0x1C))
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#define reg_pwm_stat RS_SOC_REG32(RS_SOC_APB_PWM_BASE, UINT32_C(0x20))
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// ps2
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#define reg_ps2_ctrl RS_SOC_REG32(RS_SOC_APB_PS2_BASE, UINT32_C(0x00))
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#define reg_ps2_data RS_SOC_REG32(RS_SOC_APB_PS2_BASE, UINT32_C(0x04))
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#define reg_ps2_stat RS_SOC_REG32(RS_SOC_APB_PS2_BASE, UINT32_C(0x08))
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// rtc
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#define reg_rtc_ctrl RS_SOC_REG32(RS_SOC_APB_RTC_BASE, UINT32_C(0x00))
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#define reg_rtc_pscr RS_SOC_REG32(RS_SOC_APB_RTC_BASE, UINT32_C(0x04))
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#define reg_rtc_cnt RS_SOC_REG32(RS_SOC_APB_RTC_BASE, UINT32_C(0x08))
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#define reg_rtc_alrm RS_SOC_REG32(RS_SOC_APB_RTC_BASE, UINT32_C(0x0C))
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#define reg_rtc_ista RS_SOC_REG32(RS_SOC_APB_RTC_BASE, UINT32_C(0x10))
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#define reg_rtc_ssta RS_SOC_REG32(RS_SOC_APB_RTC_BASE, UINT32_C(0x14))
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// wdg
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#define reg_wdg_ctrl RS_SOC_REG32(RS_SOC_APB_WDG_BASE, UINT32_C(0x00))
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#define reg_wdg_pscr RS_SOC_REG32(RS_SOC_APB_WDG_BASE, UINT32_C(0x04))
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#define reg_wdg_cnt RS_SOC_REG32(RS_SOC_APB_WDG_BASE, UINT32_C(0x08))
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#define reg_wdg_cmp RS_SOC_REG32(RS_SOC_APB_WDG_BASE, UINT32_C(0x0C))
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#define reg_wdg_stat RS_SOC_REG32(RS_SOC_APB_WDG_BASE, UINT32_C(0x10))
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#define reg_wdg_key RS_SOC_REG32(RS_SOC_APB_WDG_BASE, UINT32_C(0x14))
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#define reg_wdg_feed RS_SOC_REG32(RS_SOC_APB_WDG_BASE, UINT32_C(0x18))
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// crc
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#define reg_crc_ctrl RS_SOC_REG32(RS_SOC_APB_CRC_BASE, UINT32_C(0x00))
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#define reg_crc_init RS_SOC_REG32(RS_SOC_APB_CRC_BASE, UINT32_C(0x04))
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#define reg_crc_xorv RS_SOC_REG32(RS_SOC_APB_CRC_BASE, UINT32_C(0x08))
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#define reg_crc_data RS_SOC_REG32(RS_SOC_APB_CRC_BASE, UINT32_C(0x0C))
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#define reg_crc_stat RS_SOC_REG32(RS_SOC_APB_CRC_BASE, UINT32_C(0x10))
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// tim3
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#define reg_tim3_ctrl RS_SOC_REG32(RS_SOC_APB_TMR_BASE, UINT32_C(0x00))
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#define reg_tim3_pscr RS_SOC_REG32(RS_SOC_APB_TMR_BASE, UINT32_C(0x04))
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#define reg_tim3_cnt RS_SOC_REG32(RS_SOC_APB_TMR_BASE, UINT32_C(0x08))
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#define reg_tim3_cmp RS_SOC_REG32(RS_SOC_APB_TMR_BASE, UINT32_C(0x0C))
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#define reg_tim3_stat RS_SOC_REG32(RS_SOC_APB_TMR_BASE, UINT32_C(0x10))
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#define reg_user_ip_reg0 RS_SOC_REG32(RS_SOC_APB_USER_IP_BASE, UINT32_C(0x00))
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#define reg_user_ip_reg1 RS_SOC_REG32(RS_SOC_APB_USER_IP_BASE, UINT32_C(0x04))
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#define reg_user_ip_reg2 RS_SOC_REG32(RS_SOC_APB_USER_IP_BASE, UINT32_C(0x08))
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#define reg_user_ip_reg3 RS_SOC_REG32(RS_SOC_APB_USER_IP_BASE, UINT32_C(0x0C))
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#define reg_user_ip_reg4 RS_SOC_REG32(RS_SOC_APB_USER_IP_BASE, UINT32_C(0x10))
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#define reg_user_ip_reg5 RS_SOC_REG32(RS_SOC_APB_USER_IP_BASE, UINT32_C(0x14))
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#define reg_user_ip_reg6 RS_SOC_REG32(RS_SOC_APB_USER_IP_BASE, UINT32_C(0x18))
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#endif
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