mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
3aa3d937e1
- Updated filelist to include new timer peripheral files. - Enhanced formal file generation script to support timer target. - Created timer formal design and properties for formal verification. - Modified formal makefile to include timer targets and source files. - Added timer-related source files to software makefile. - Updated core and management wrappers to include debug halted signal. - Implemented timer testbench for RTL simulation. - Added regression tests for timer functionality in Python. - Introduced timer helper functions in C tests for validation.
32 lines
1.2 KiB
Systemverilog
32 lines
1.2 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
|
|
// retroSoC is licensed under Mulan PSL v2.
|
|
|
|
`ifndef RIBP_TIMER_DEFINE_SVH
|
|
`define RIBP_TIMER_DEFINE_SVH
|
|
|
|
// verilog_format: off
|
|
`define RIBP_TIMER_CTRL 12'h000
|
|
`define RIBP_TIMER_LOAD 12'h004
|
|
`define RIBP_TIMER_VALUE 12'h008
|
|
`define RIBP_TIMER_BGLOAD 12'h00C
|
|
`define RIBP_TIMER_PRESCALE 12'h010
|
|
`define RIBP_TIMER_COMPARE0 12'h014
|
|
`define RIBP_TIMER_COMPARE1 12'h018
|
|
`define RIBP_TIMER_STATUS 12'h01C
|
|
`define RIBP_TIMER_INTR_STATE 12'h020
|
|
`define RIBP_TIMER_INTR_ENABLE 12'h024
|
|
`define RIBP_TIMER_INTR_STATUS 12'h028
|
|
`define RIBP_TIMER_INTR_TEST 12'h02C
|
|
`define RIBP_TIMER_IP_VERSION 12'h0F8
|
|
`define RIBP_TIMER_CAPABILITY 12'h0FC
|
|
|
|
`define TIMER_CTRL_ENABLE 0
|
|
`define TIMER_CTRL_MODE 1
|
|
`define TIMER_CTRL_DIRECTION 3
|
|
`define TIMER_CTRL_DEBUG_FREEZE 4
|
|
`define TIMER_CTRL_COMPARE0_ENABLE 5
|
|
`define TIMER_CTRL_COMPARE1_ENABLE 6
|
|
// verilog_format: on
|
|
|
|
`endif
|