mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-05 06:32:37 +00:00
maksyuki
3aa3d937e1
- Updated filelist to include new timer peripheral files. - Enhanced formal file generation script to support timer target. - Created timer formal design and properties for formal verification. - Modified formal makefile to include timer targets and source files. - Added timer-related source files to software makefile. - Updated core and management wrappers to include debug halted signal. - Implemented timer testbench for RTL simulation. - Added regression tests for timer functionality in Python. - Introduced timer helper functions in C tests for validation.
84 lines
2.5 KiB
Systemverilog
84 lines
2.5 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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module timer_formal_design (
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// verilog_format: off
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input logic clk_i,
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output logic rst_n_i,
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output logic f_past_valid,
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output logic rib_valid,
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output logic [31:0] rib_addr,
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output logic [31:0] rib_wdata,
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output logic [ 3:0] rib_wstrb,
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output logic rib_ready,
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output logic rib_resp_err,
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output logic debug_halted,
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output logic active,
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output logic debug_frozen,
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output logic [31:0] value,
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output logic start,
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output logic stop,
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output logic load_now,
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output logic timeout_event,
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output logic compare0_event,
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output logic compare1_event,
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output logic one_shot_done,
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output logic [ 2:0] intr_state,
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output logic [ 2:0] intr_enable,
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output logic irq
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// verilog_format: on
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);
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ribp_if rib ();
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(* anyseq *)logic f_rib_valid;
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(* anyseq *)logic [31:0] f_rib_addr;
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(* anyseq *)logic [31:0] f_rib_wdata;
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(* anyseq *)logic [ 3:0] f_rib_wstrb;
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(* anyseq *)logic f_debug_halted;
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assign rib.valid = f_rib_valid;
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assign rib.addr = f_rib_addr;
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assign rib.wdata = f_rib_wdata;
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assign rib.wstrb = f_rib_wstrb;
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assign rib_valid = rib.valid;
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assign rib_addr = rib.addr;
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assign rib_wdata = rib.wdata;
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assign rib_wstrb = rib.wstrb;
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assign rib_ready = rib.ready;
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assign rib_resp_err = rib.resp_err;
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assign debug_halted = f_debug_halted;
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assign active = u_dut.s_enable;
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assign debug_frozen = u_dut.s_debug_frozen;
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assign value = u_dut.s_value;
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assign start = u_dut.s_start;
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assign stop = u_dut.s_stop;
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assign load_now = u_dut.s_load_now;
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assign timeout_event = u_dut.s_timeout_event;
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assign compare0_event = u_dut.s_compare0_event;
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assign compare1_event = u_dut.s_compare1_event;
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assign one_shot_done = u_dut.s_one_shot_done;
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assign intr_state = u_dut.u_timer_reg.s_intr_state_q;
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assign intr_enable = u_dut.u_timer_reg.s_intr_enable_q;
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ribp_timer u_dut (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.debug_halted_i(f_debug_halted),
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.ribp (rib),
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.irq_o (irq)
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);
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initial begin
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rst_n_i = 1'b0;
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f_past_valid = 1'b0;
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end
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always_ff @(posedge clk_i) begin
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rst_n_i <= 1'b1;
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f_past_valid <= 1'b1;
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end
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endmodule
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