0 Fork 0

mirror of https://github.com/retroSoC/retroSoC.git synced 2026-11-04 22:32:36 +00:00

Files

T

maksyuki 3ac9e73ab9 feat: refactor tests for mailbox and environment validation

- Updated mailbox purpose tests to reflect new write order and sequence handling.
- Added tests to ensure Linux-ready values match LP contract and constants match Linux helper.
- Introduced tests to verify that offset changes do not hide stale Linux helpers.
- Enhanced environment tests to report current locked launcher and runtime versions.
- Added checks for SBT launcher presence in environment labels.
- Improved full diagram tests to validate storage geometry and RSA vector configurations.
- Expanded register tests to ensure crypto interrupt registers publish all events and lifecycle annotations preserve security boundaries.
- Modified script tools tests to include Vexii generation validation and updated workflow assertions.

2026-09-30 10:51:04 +08:00

bondpad

feat: Add IHP130 support and enhance power pin handling

2026-08-23 22:27:04 +08:00

mini

feat(tiny): add scripts for SDC generation and packaging

2026-09-27 08:48:12 +08:00

tiny

feat: refactor tests for mailbox and environment validation

2026-09-30 10:51:04 +08:00

README.md

feat(tiny): add scripts for SDC generation and packaging

2026-09-27 08:48:12 +08:00

README.md

LibreLane IHP130 Flows

This directory groups the open-source LibreLane/IHP130 implementation flows by product line:

mini/ hardens the Mini SoC deliverables (retrosoc_core padless macro and the bare-die retrosoc_asic pad-ring chip) for SOC=MINI profiles such as configs/ci/ihp130.mk.
tiny/ implements the bare-die Tiny MCU (retrosoc_tiny_asic, pad-ring chip only) for SOC=TINY with configs/ci/ihp130-tiny.mk.
bondpad/ holds the shared 70 um bondpad LEF collateral used by both chip flows.

The top-level Makefile includes mini/Makefile or tiny/Makefile according to SOC, so the target names (librelane-doctor, librelane-chip, librelane-package, and the Mini-only librelane-core) are uniform across product lines.

Both lines require the LibreLane 3.0.5 development environment, the locked IHP-Open-PDK checkout under physical/pdk/, and the locked OpenSTA 3.0.0. PDK=GF180, PDK=SKY130, and PDK=ICS55 are intentionally rejected until their technology-specific LibreLane adapters, pad cells, macro collateral, and signoff decks are qualified.

A successful open-source run is evidence for implementation development, not a foundry production-signoff claim. Release review still requires qualified foundry decks, package and bond planning, electrical/ESD review, and approved waivers.