mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
3ac9e73ab9
- Updated mailbox purpose tests to reflect new write order and sequence handling. - Added tests to ensure Linux-ready values match LP contract and constants match Linux helper. - Introduced tests to verify that offset changes do not hide stale Linux helpers. - Enhanced environment tests to report current locked launcher and runtime versions. - Added checks for SBT launcher presence in environment labels. - Improved full diagram tests to validate storage geometry and RSA vector configurations. - Expanded register tests to ensure crypto interrupt registers publish all events and lifecycle annotations preserve security boundaries. - Modified script tools tests to include Vexii generation validation and updated workflow assertions.
12738 lines
309 KiB
JSON
12738 lines
309 KiB
JSON
{
|
|
"gpio": {
|
|
"nodes": [
|
|
{
|
|
"id": "apb",
|
|
"title": "APB4 control\n32-bit register access",
|
|
"x": 0.0,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/peripheral/apb4_gpio.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "reg",
|
|
"title": "Register bank\nconfiguration / status",
|
|
"x": 0.0,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "east"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/peripheral/apb4_gpio.sv",
|
|
"rtl/ip/peripheral/gpio_reg.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/peripheral/apb4_gpio.sv",
|
|
"name": "u_gpio_reg",
|
|
"module": "gpio_reg",
|
|
"declaration_file": "rtl/ip/peripheral/gpio_reg.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "core",
|
|
"title": "Input filtering\nGPIO mux / pad control",
|
|
"x": 6.3,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p1",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p3",
|
|
"direction": "out",
|
|
"width": null,
|
|
"side": "east",
|
|
"bundle": true
|
|
},
|
|
{
|
|
"id": "p4",
|
|
"direction": "in",
|
|
"width": null,
|
|
"side": "south",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/peripheral/apb4_gpio.sv",
|
|
"rtl/ip/peripheral/gpio_core.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/peripheral/apb4_gpio.sv",
|
|
"name": "u_gpio_core",
|
|
"module": "gpio_core",
|
|
"declaration_file": "rtl/ip/peripheral/gpio_core.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "pads",
|
|
"title": "GPIO pad interface\n32 digital pins",
|
|
"x": 12.6,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p3",
|
|
"direction": "in",
|
|
"width": null,
|
|
"side": "west",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/peripheral/apb4_gpio.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "user",
|
|
"title": "User GPIO interface\nselected handoff",
|
|
"x": 6.3,
|
|
"y": 0.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p4",
|
|
"direction": "out",
|
|
"width": null,
|
|
"side": "north",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/peripheral/apb4_gpio.sv"
|
|
]
|
|
}
|
|
],
|
|
"edges": [
|
|
{
|
|
"from": "apb.p0",
|
|
"to": "reg.p0",
|
|
"kind": "data",
|
|
"label": "APB4 / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_gpio.sv",
|
|
"text": ".apb4(apb4)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "apb4",
|
|
"expression": "apb4"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "reg.p1",
|
|
"to": "core.p1",
|
|
"kind": "data",
|
|
"label": "OUT / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_gpio.sv",
|
|
"text": ".data_out_o(s_data_out)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_gpio.sv",
|
|
"text": ".data_out_i(s_data_out)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_gpio.sv",
|
|
"scope": "apb4_gpio",
|
|
"symbol": "s_data_out",
|
|
"bits": 32
|
|
},
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_gpio.sv",
|
|
"scope": "apb4_gpio",
|
|
"symbol": "s_data_out",
|
|
"bits": 32
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "data_out_o",
|
|
"expression": "s_data_out"
|
|
},
|
|
{
|
|
"node": "core",
|
|
"port": "data_out_i",
|
|
"expression": "s_data_out"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "core.p2",
|
|
"to": "reg.p2",
|
|
"kind": "data",
|
|
"label": "IN / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_gpio.sv",
|
|
"text": ".data_in_o(s_data_in)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_gpio.sv",
|
|
"text": ".data_in_i(s_data_in)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_gpio.sv",
|
|
"scope": "apb4_gpio",
|
|
"symbol": "s_data_in",
|
|
"bits": 32
|
|
},
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_gpio.sv",
|
|
"scope": "apb4_gpio",
|
|
"symbol": "s_data_in",
|
|
"bits": 32
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "data_in_o",
|
|
"expression": "s_data_in"
|
|
},
|
|
{
|
|
"node": "reg",
|
|
"port": "data_in_i",
|
|
"expression": "s_data_in"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "core.p3",
|
|
"to": "pads.p3",
|
|
"kind": "data",
|
|
"label": "GPIO",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_gpio.sv",
|
|
"text": ".gpio(gpio)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "gpio",
|
|
"expression": "gpio"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "user.p4",
|
|
"to": "core.p4",
|
|
"kind": "data",
|
|
"label": "User GPIO",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_gpio.sv",
|
|
"text": ".user_gpio(user_gpio)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "user_gpio",
|
|
"expression": "user_gpio"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
}
|
|
],
|
|
"note": "Selected implementation paths; unshown handshakes, reset and IRQ details remain in the interface contract."
|
|
},
|
|
"timer": {
|
|
"nodes": [
|
|
{
|
|
"id": "apb",
|
|
"title": "APB4 control\n32-bit register access",
|
|
"x": 0.0,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/peripheral/apb4_timer.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "reg",
|
|
"title": "Register bank\nconfiguration / status",
|
|
"x": 0.0,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "east"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/peripheral/apb4_timer.sv",
|
|
"rtl/ip/peripheral/timer_reg.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/peripheral/apb4_timer.sv",
|
|
"name": "u_timer_reg",
|
|
"module": "timer_reg",
|
|
"declaration_file": "rtl/ip/peripheral/timer_reg.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "core",
|
|
"title": "Timer channel\nprescaler / compare",
|
|
"x": 6.3,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p1",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p3",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/peripheral/apb4_timer.sv",
|
|
"rtl/ip/peripheral/timer_core.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/peripheral/apb4_timer.sv",
|
|
"name": "u_timer_core",
|
|
"module": "timer_core",
|
|
"declaration_file": "rtl/ip/peripheral/timer_core.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "debug",
|
|
"title": "Debug halt input",
|
|
"x": 12.6,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p3",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "west"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/peripheral/apb4_timer.sv"
|
|
]
|
|
}
|
|
],
|
|
"edges": [
|
|
{
|
|
"from": "apb.p0",
|
|
"to": "reg.p0",
|
|
"kind": "data",
|
|
"label": "APB4 / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_timer.sv",
|
|
"text": ".apb4(apb4)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "apb4",
|
|
"expression": "apb4"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "reg.p1",
|
|
"to": "core.p1",
|
|
"kind": "data",
|
|
"label": "LOAD / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_timer.sv",
|
|
"text": ".load_o(s_load)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_timer.sv",
|
|
"text": ".load_i(s_load)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_timer.sv",
|
|
"scope": "apb4_timer",
|
|
"symbol": "s_load",
|
|
"bits": 32
|
|
},
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_timer.sv",
|
|
"scope": "apb4_timer",
|
|
"symbol": "s_load",
|
|
"bits": 32
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "load_o",
|
|
"expression": "s_load"
|
|
},
|
|
{
|
|
"node": "core",
|
|
"port": "load_i",
|
|
"expression": "s_load"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "core.p2",
|
|
"to": "reg.p2",
|
|
"kind": "control",
|
|
"label": "TIMEOUT",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_timer.sv",
|
|
"text": ".timeout_event_o(s_timeout_event)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_timer.sv",
|
|
"text": ".timeout_event_i(s_timeout_event)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_timer.sv",
|
|
"scope": "apb4_timer",
|
|
"symbol": "s_timeout_event",
|
|
"bits": 1
|
|
},
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_timer.sv",
|
|
"scope": "apb4_timer",
|
|
"symbol": "s_timeout_event",
|
|
"bits": 1
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "timeout_event_o",
|
|
"expression": "s_timeout_event"
|
|
},
|
|
{
|
|
"node": "reg",
|
|
"port": "timeout_event_i",
|
|
"expression": "s_timeout_event"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "debug.p3",
|
|
"to": "core.p3",
|
|
"kind": "control",
|
|
"label": "HALTED",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_timer.sv",
|
|
"text": ".debug_halted_i(debug_halted_i)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_timer.sv",
|
|
"scope": "apb4_timer",
|
|
"symbol": "debug_halted_i",
|
|
"bits": 1
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "debug_halted_i",
|
|
"expression": "debug_halted_i"
|
|
}
|
|
]
|
|
}
|
|
],
|
|
"note": "TIM0 and TIM1 each instantiate this channel. Two compare events and debug-freeze policy are local to each timer; shared diagrams do not imply shared counter state."
|
|
},
|
|
"ws2812": {
|
|
"nodes": [
|
|
{
|
|
"id": "apb",
|
|
"title": "APB4 control\n32-bit register access",
|
|
"x": 0.0,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/serial/apb4_ws2812.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "reg",
|
|
"title": "Register bank\nconfiguration / status",
|
|
"x": 0.0,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "out",
|
|
"width": 24,
|
|
"side": "east"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/serial/apb4_ws2812.sv",
|
|
"rtl/ip/serial/ws2812_reg.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/serial/apb4_ws2812.sv",
|
|
"name": "u_ws2812_reg",
|
|
"module": "ws2812_reg",
|
|
"declaration_file": "rtl/ip/serial/ws2812_reg.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "core",
|
|
"title": "Bit-period engine\nframe / reset sequencer",
|
|
"x": 6.3,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p1",
|
|
"direction": "in",
|
|
"width": 24,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p3",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/serial/apb4_ws2812.sv",
|
|
"rtl/ip/serial/ws2812_core.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/serial/apb4_ws2812.sv",
|
|
"name": "u_ws2812_core",
|
|
"module": "ws2812_core",
|
|
"declaration_file": "rtl/ip/serial/ws2812_core.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "pads",
|
|
"title": "WS2812 data output",
|
|
"x": 12.6,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p3",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "west"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/serial/apb4_ws2812.sv"
|
|
]
|
|
}
|
|
],
|
|
"edges": [
|
|
{
|
|
"from": "apb.p0",
|
|
"to": "reg.p0",
|
|
"kind": "data",
|
|
"label": "APB4 / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/serial/apb4_ws2812.sv",
|
|
"text": ".apb4(apb4)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "apb4",
|
|
"expression": "apb4"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "reg.p1",
|
|
"to": "core.p1",
|
|
"kind": "data",
|
|
"label": "PIXEL / 24",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/serial/apb4_ws2812.sv",
|
|
"text": ".data_o(s_data)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/serial/apb4_ws2812.sv",
|
|
"text": ".data_i(s_data)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/serial/apb4_ws2812.sv",
|
|
"scope": "apb4_ws2812",
|
|
"symbol": "s_data",
|
|
"bits": 24
|
|
},
|
|
{
|
|
"file": "rtl/ip/serial/apb4_ws2812.sv",
|
|
"scope": "apb4_ws2812",
|
|
"symbol": "s_data",
|
|
"bits": 24
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "data_o",
|
|
"expression": "s_data"
|
|
},
|
|
{
|
|
"node": "core",
|
|
"port": "data_i",
|
|
"expression": "s_data"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "core.p2",
|
|
"to": "reg.p2",
|
|
"kind": "control",
|
|
"label": "POP",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/serial/apb4_ws2812.sv",
|
|
"text": ".data_pop_o(s_data_pop)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/serial/apb4_ws2812.sv",
|
|
"text": ".data_pop_i(s_data_pop)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/serial/apb4_ws2812.sv",
|
|
"scope": "apb4_ws2812",
|
|
"symbol": "s_data_pop",
|
|
"bits": 1
|
|
},
|
|
{
|
|
"file": "rtl/ip/serial/apb4_ws2812.sv",
|
|
"scope": "apb4_ws2812",
|
|
"symbol": "s_data_pop",
|
|
"bits": 1
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "data_pop_o",
|
|
"expression": "s_data_pop"
|
|
},
|
|
{
|
|
"node": "reg",
|
|
"port": "data_pop_i",
|
|
"expression": "s_data_pop"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "core.p3",
|
|
"to": "pads.p3",
|
|
"kind": "data",
|
|
"label": "DATA",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/serial/apb4_ws2812.sv",
|
|
"text": ".dat_o(s_dat)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/serial/apb4_ws2812.sv",
|
|
"scope": "apb4_ws2812",
|
|
"symbol": "s_dat",
|
|
"bits": 1
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "dat_o",
|
|
"expression": "s_dat"
|
|
}
|
|
]
|
|
}
|
|
],
|
|
"note": "Selected implementation paths; unshown handshakes, reset and IRQ details remain in the interface contract."
|
|
},
|
|
"i2c": {
|
|
"nodes": [
|
|
{
|
|
"id": "apb",
|
|
"title": "APB4 control\n32-bit register access",
|
|
"x": 0.0,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/serial/apb4_i2c.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "reg",
|
|
"title": "Register bank\nconfiguration / status",
|
|
"x": 0.0,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "out",
|
|
"width": 12,
|
|
"side": "east"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "in",
|
|
"width": 8,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/serial/apb4_i2c.sv",
|
|
"rtl/ip/serial/i2c_reg.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/serial/apb4_i2c.sv",
|
|
"name": "u_i2c_reg",
|
|
"module": "i2c_reg",
|
|
"declaration_file": "rtl/ip/serial/i2c_reg.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "core",
|
|
"title": "I2C command engine\nSCL / SDA timing",
|
|
"x": 6.3,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p1",
|
|
"direction": "in",
|
|
"width": 12,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "out",
|
|
"width": 8,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p3",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "east"
|
|
},
|
|
{
|
|
"id": "p5",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/serial/apb4_i2c.sv",
|
|
"rtl/ip/serial/i2c_core.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/serial/apb4_i2c.sv",
|
|
"name": "u_i2c_core",
|
|
"module": "i2c_core",
|
|
"declaration_file": "rtl/ip/serial/i2c_core.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "filter",
|
|
"title": "Input synchronizer\nSCL / SDA filters",
|
|
"x": 12.6,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p3",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p4",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/serial/apb4_i2c.sv",
|
|
"rtl/ip/serial/i2c_filter.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/serial/apb4_i2c.sv",
|
|
"name": "u_i2c_filter",
|
|
"module": "i2c_filter",
|
|
"declaration_file": "rtl/ip/serial/i2c_filter.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "pads",
|
|
"title": "Open-drain\nSCL / SDA pads",
|
|
"x": 12.6,
|
|
"y": 0.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p4",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p5",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "north"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/serial/apb4_i2c.sv"
|
|
]
|
|
}
|
|
],
|
|
"edges": [
|
|
{
|
|
"from": "apb.p0",
|
|
"to": "reg.p0",
|
|
"kind": "data",
|
|
"label": "APB4 / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/serial/apb4_i2c.sv",
|
|
"text": ".apb4(apb4)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "apb4",
|
|
"expression": "apb4"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "reg.p1",
|
|
"to": "core.p1",
|
|
"kind": "data",
|
|
"label": "CMD / 12",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/serial/apb4_i2c.sv",
|
|
"text": ".cmd_data_o(s_cmd_data)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/serial/apb4_i2c.sv",
|
|
"text": ".cmd_data_i(s_cmd_data)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/serial/apb4_i2c.sv",
|
|
"scope": "apb4_i2c",
|
|
"symbol": "s_cmd_data",
|
|
"bits": 12
|
|
},
|
|
{
|
|
"file": "rtl/ip/serial/apb4_i2c.sv",
|
|
"scope": "apb4_i2c",
|
|
"symbol": "s_cmd_data",
|
|
"bits": 12
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "cmd_data_o",
|
|
"expression": "s_cmd_data"
|
|
},
|
|
{
|
|
"node": "core",
|
|
"port": "cmd_data_i",
|
|
"expression": "s_cmd_data"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "core.p2",
|
|
"to": "reg.p2",
|
|
"kind": "data",
|
|
"label": "RX / 8",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/serial/apb4_i2c.sv",
|
|
"text": ".rx_data_o(s_rx_data)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/serial/apb4_i2c.sv",
|
|
"text": ".rx_data_i(s_rx_data)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/serial/apb4_i2c.sv",
|
|
"scope": "apb4_i2c",
|
|
"symbol": "s_rx_data",
|
|
"bits": 8
|
|
},
|
|
{
|
|
"file": "rtl/ip/serial/apb4_i2c.sv",
|
|
"scope": "apb4_i2c",
|
|
"symbol": "s_rx_data",
|
|
"bits": 8
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "rx_data_o",
|
|
"expression": "s_rx_data"
|
|
},
|
|
{
|
|
"node": "reg",
|
|
"port": "rx_data_i",
|
|
"expression": "s_rx_data"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "filter.p3",
|
|
"to": "core.p3",
|
|
"kind": "data",
|
|
"label": "SDA sample",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/serial/apb4_i2c.sv",
|
|
"text": ".sda_o(s_sda_filtered)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/serial/apb4_i2c.sv",
|
|
"text": ".sda_i(s_sda_filtered)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/serial/apb4_i2c.sv",
|
|
"scope": "apb4_i2c",
|
|
"symbol": "s_sda_filtered",
|
|
"bits": 1
|
|
},
|
|
{
|
|
"file": "rtl/ip/serial/apb4_i2c.sv",
|
|
"scope": "apb4_i2c",
|
|
"symbol": "s_sda_filtered",
|
|
"bits": 1
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "filter",
|
|
"port": "sda_o",
|
|
"expression": "s_sda_filtered"
|
|
},
|
|
{
|
|
"node": "core",
|
|
"port": "sda_i",
|
|
"expression": "s_sda_filtered"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "pads.p4",
|
|
"to": "filter.p4",
|
|
"kind": "data",
|
|
"label": "SDA input",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/serial/apb4_i2c.sv",
|
|
"text": ".sda_async_i(i2c.sda_i)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "filter",
|
|
"port": "sda_async_i",
|
|
"expression": "i2c.sda_i"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "core.p5",
|
|
"to": "pads.p5",
|
|
"kind": "control",
|
|
"label": "SDA pull low",
|
|
"style": "zigzag",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/serial/apb4_i2c.sv",
|
|
"text": ".sda_pull_low_o(s_sda_pull_low)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/serial/apb4_i2c.sv",
|
|
"scope": "apb4_i2c",
|
|
"symbol": "s_sda_pull_low",
|
|
"bits": 1
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "sda_pull_low_o",
|
|
"expression": "s_sda_pull_low"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
}
|
|
],
|
|
"note": "I2C0 and I2C1 each use this controller. Open-drain outputs and sampled inputs are separate; clock stretching and timeout rules remain in the protocol description."
|
|
},
|
|
"spisd": {
|
|
"nodes": [
|
|
{
|
|
"id": "apb",
|
|
"title": "APB4 control\n32-bit register access",
|
|
"x": 0.0,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/storage/apb4_spisd.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "reg",
|
|
"title": "Register bank\nconfiguration / status",
|
|
"x": 0.0,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "east"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/storage/apb4_spisd.sv",
|
|
"rtl/ip/storage/spisd_reg.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/storage/apb4_spisd.sv",
|
|
"name": "u_spisd_reg",
|
|
"module": "spisd_reg",
|
|
"declaration_file": "rtl/ip/storage/spisd_reg.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "core",
|
|
"title": "SPI-mode SD engine\nPIO / DMA sequencing",
|
|
"x": 6.3,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p1",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p3",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "south"
|
|
},
|
|
{
|
|
"id": "p4",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "east"
|
|
},
|
|
{
|
|
"id": "p5",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/storage/apb4_spisd.sv",
|
|
"rtl/ip/storage/spisd_core.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/storage/apb4_spisd.sv",
|
|
"name": "u_spisd_core",
|
|
"module": "spisd_core",
|
|
"declaration_file": "rtl/ip/storage/spisd_core.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "memory",
|
|
"title": "Private AXI32 DMA\nshared memory fabric",
|
|
"x": 6.3,
|
|
"y": 0.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p3",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "north"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/storage/apb4_spisd.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "pads",
|
|
"title": "SD card pads\nSPI interface",
|
|
"x": 12.6,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p4",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p5",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "west"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/storage/apb4_spisd.sv"
|
|
]
|
|
}
|
|
],
|
|
"edges": [
|
|
{
|
|
"from": "apb.p0",
|
|
"to": "reg.p0",
|
|
"kind": "data",
|
|
"label": "APB4 / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/storage/apb4_spisd.sv",
|
|
"text": ".apb4(apb4)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "apb4",
|
|
"expression": "apb4"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "reg.p1",
|
|
"to": "core.p1",
|
|
"kind": "data",
|
|
"label": "ARG / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/storage/apb4_spisd.sv",
|
|
"text": ".cmd_arg_o(s_cmd_arg)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/storage/apb4_spisd.sv",
|
|
"text": ".cmd_arg_i(s_cmd_arg)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/storage/apb4_spisd.sv",
|
|
"scope": "apb4_spisd",
|
|
"symbol": "s_cmd_arg",
|
|
"bits": 32
|
|
},
|
|
{
|
|
"file": "rtl/ip/storage/apb4_spisd.sv",
|
|
"scope": "apb4_spisd",
|
|
"symbol": "s_cmd_arg",
|
|
"bits": 32
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "cmd_arg_o",
|
|
"expression": "s_cmd_arg"
|
|
},
|
|
{
|
|
"node": "core",
|
|
"port": "cmd_arg_i",
|
|
"expression": "s_cmd_arg"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "core.p2",
|
|
"to": "reg.p2",
|
|
"kind": "data",
|
|
"label": "PIO RX / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/storage/apb4_spisd.sv",
|
|
"text": ".pio_rdata_o(s_pio_rdata)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/storage/apb4_spisd.sv",
|
|
"text": ".pio_rdata_i(s_pio_rdata)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/storage/apb4_spisd.sv",
|
|
"scope": "apb4_spisd",
|
|
"symbol": "s_pio_rdata",
|
|
"bits": 32
|
|
},
|
|
{
|
|
"file": "rtl/ip/storage/apb4_spisd.sv",
|
|
"scope": "apb4_spisd",
|
|
"symbol": "s_pio_rdata",
|
|
"bits": 32
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "pio_rdata_o",
|
|
"expression": "s_pio_rdata"
|
|
},
|
|
{
|
|
"node": "reg",
|
|
"port": "pio_rdata_i",
|
|
"expression": "s_pio_rdata"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "core.p3",
|
|
"to": "memory.p3",
|
|
"kind": "data",
|
|
"label": "AXI4 / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/storage/apb4_spisd.sv",
|
|
"text": ".dma_axi4(dma_axi4)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "dma_axi4",
|
|
"expression": "dma_axi4"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "core.p4",
|
|
"to": "pads.p4",
|
|
"kind": "data",
|
|
"label": "MOSI",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/storage/apb4_spisd.sv",
|
|
"text": ".mosi_o(spi.mosi_o)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "mosi_o",
|
|
"expression": "spi.mosi_o"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "pads.p5",
|
|
"to": "core.p5",
|
|
"kind": "data",
|
|
"label": "MISO",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/storage/apb4_spisd.sv",
|
|
"text": ".miso_i(spi.miso_i)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "miso_i",
|
|
"expression": "spi.miso_i"
|
|
}
|
|
]
|
|
}
|
|
],
|
|
"note": "Selected controller paths. Descriptor, byte-lane and command ordering are separate formats. SPI-mode SD uses its private AXI32 DMA path."
|
|
},
|
|
"sdio0": {
|
|
"nodes": [
|
|
{
|
|
"id": "apb",
|
|
"title": "APB4 control\n32-bit register access",
|
|
"x": 0.0,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/storage/apb4_sdio.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "reg",
|
|
"title": "Register bank\nconfiguration / status",
|
|
"x": 0.0,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "east"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/storage/apb4_sdio.sv",
|
|
"rtl/ip/storage/sdio_reg.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/storage/apb4_sdio.sv",
|
|
"name": "u_sdio_reg",
|
|
"module": "sdio_reg",
|
|
"declaration_file": "rtl/ip/storage/sdio_reg.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "core",
|
|
"title": "Native SD command / data\nPIO / DMA sequencing",
|
|
"x": 6.3,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p1",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p3",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "south"
|
|
},
|
|
{
|
|
"id": "p4",
|
|
"direction": "out",
|
|
"width": null,
|
|
"side": "east",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/storage/apb4_sdio.sv",
|
|
"rtl/ip/storage/sdio_core.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/storage/apb4_sdio.sv",
|
|
"name": "u_sdio_core",
|
|
"module": "sdio_core",
|
|
"declaration_file": "rtl/ip/storage/sdio_core.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "memory",
|
|
"title": "Private AXI32 DMA\nshared memory fabric",
|
|
"x": 6.3,
|
|
"y": 0.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p3",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "north"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/storage/apb4_sdio.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "pads",
|
|
"title": "SD card pads\n1-bit / 4-bit data",
|
|
"x": 12.6,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p4",
|
|
"direction": "in",
|
|
"width": null,
|
|
"side": "west",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/storage/apb4_sdio.sv"
|
|
]
|
|
}
|
|
],
|
|
"edges": [
|
|
{
|
|
"from": "apb.p0",
|
|
"to": "reg.p0",
|
|
"kind": "data",
|
|
"label": "APB4 / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/storage/apb4_sdio.sv",
|
|
"text": ".apb4(apb4)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "apb4",
|
|
"expression": "apb4"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "reg.p1",
|
|
"to": "core.p1",
|
|
"kind": "data",
|
|
"label": "ARG / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/storage/apb4_sdio.sv",
|
|
"text": ".cmd_arg_o(s_cmd_arg)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/storage/apb4_sdio.sv",
|
|
"text": ".cmd_arg_i(s_cmd_arg)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/storage/apb4_sdio.sv",
|
|
"scope": "apb4_sdio",
|
|
"symbol": "s_cmd_arg",
|
|
"bits": 32
|
|
},
|
|
{
|
|
"file": "rtl/ip/storage/apb4_sdio.sv",
|
|
"scope": "apb4_sdio",
|
|
"symbol": "s_cmd_arg",
|
|
"bits": 32
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "cmd_arg_o",
|
|
"expression": "s_cmd_arg"
|
|
},
|
|
{
|
|
"node": "core",
|
|
"port": "cmd_arg_i",
|
|
"expression": "s_cmd_arg"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "core.p2",
|
|
"to": "reg.p2",
|
|
"kind": "data",
|
|
"label": "PIO RX / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/storage/apb4_sdio.sv",
|
|
"text": ".pio_rdata_o(s_pio_rdata)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/storage/apb4_sdio.sv",
|
|
"text": ".pio_rdata_i(s_pio_rdata)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/storage/apb4_sdio.sv",
|
|
"scope": "apb4_sdio",
|
|
"symbol": "s_pio_rdata",
|
|
"bits": 32
|
|
},
|
|
{
|
|
"file": "rtl/ip/storage/apb4_sdio.sv",
|
|
"scope": "apb4_sdio",
|
|
"symbol": "s_pio_rdata",
|
|
"bits": 32
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "pio_rdata_o",
|
|
"expression": "s_pio_rdata"
|
|
},
|
|
{
|
|
"node": "reg",
|
|
"port": "pio_rdata_i",
|
|
"expression": "s_pio_rdata"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "core.p3",
|
|
"to": "memory.p3",
|
|
"kind": "data",
|
|
"label": "AXI4 / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/storage/apb4_sdio.sv",
|
|
"text": ".dma_axi4(dma_axi4)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "dma_axi4",
|
|
"expression": "dma_axi4"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "core.p4",
|
|
"to": "pads.p4",
|
|
"kind": "data",
|
|
"label": "SD signals",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/storage/apb4_sdio.sv",
|
|
"text": "assign sdio.dat_do_o = u_sdio_core_if.dat_do_o;"
|
|
},
|
|
{
|
|
"file": "rtl/ip/storage/apb4_sdio.sv",
|
|
"text": ".sdio(u_sdio_core_if)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "sdio",
|
|
"expression": "u_sdio_core_if"
|
|
}
|
|
]
|
|
}
|
|
],
|
|
"note": "Selected controller paths. Descriptor, byte-lane and command ordering are separate formats. SDIO0 keeps its own base, pads and IRQ; the protocol and descriptor formats are shared."
|
|
},
|
|
"sdio1": {
|
|
"nodes": [
|
|
{
|
|
"id": "apb",
|
|
"title": "APB4 control\n32-bit register access",
|
|
"x": 0.0,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/storage/apb4_sdio.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "reg",
|
|
"title": "Register bank\nconfiguration / status",
|
|
"x": 0.0,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "east"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/storage/apb4_sdio.sv",
|
|
"rtl/ip/storage/sdio_reg.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/storage/apb4_sdio.sv",
|
|
"name": "u_sdio_reg",
|
|
"module": "sdio_reg",
|
|
"declaration_file": "rtl/ip/storage/sdio_reg.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "core",
|
|
"title": "Native SD command / data\nPIO / DMA sequencing",
|
|
"x": 6.3,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p1",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p3",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "south"
|
|
},
|
|
{
|
|
"id": "p4",
|
|
"direction": "out",
|
|
"width": null,
|
|
"side": "east",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/storage/apb4_sdio.sv",
|
|
"rtl/ip/storage/sdio_core.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/storage/apb4_sdio.sv",
|
|
"name": "u_sdio_core",
|
|
"module": "sdio_core",
|
|
"declaration_file": "rtl/ip/storage/sdio_core.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "memory",
|
|
"title": "Private AXI32 DMA\nshared memory fabric",
|
|
"x": 6.3,
|
|
"y": 0.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p3",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "north"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/storage/apb4_sdio.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "pads",
|
|
"title": "SD card pads\n1-bit / 4-bit data",
|
|
"x": 12.6,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p4",
|
|
"direction": "in",
|
|
"width": null,
|
|
"side": "west",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/storage/apb4_sdio.sv"
|
|
]
|
|
}
|
|
],
|
|
"edges": [
|
|
{
|
|
"from": "apb.p0",
|
|
"to": "reg.p0",
|
|
"kind": "data",
|
|
"label": "APB4 / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/storage/apb4_sdio.sv",
|
|
"text": ".apb4(apb4)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "apb4",
|
|
"expression": "apb4"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "reg.p1",
|
|
"to": "core.p1",
|
|
"kind": "data",
|
|
"label": "ARG / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/storage/apb4_sdio.sv",
|
|
"text": ".cmd_arg_o(s_cmd_arg)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/storage/apb4_sdio.sv",
|
|
"text": ".cmd_arg_i(s_cmd_arg)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/storage/apb4_sdio.sv",
|
|
"scope": "apb4_sdio",
|
|
"symbol": "s_cmd_arg",
|
|
"bits": 32
|
|
},
|
|
{
|
|
"file": "rtl/ip/storage/apb4_sdio.sv",
|
|
"scope": "apb4_sdio",
|
|
"symbol": "s_cmd_arg",
|
|
"bits": 32
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "cmd_arg_o",
|
|
"expression": "s_cmd_arg"
|
|
},
|
|
{
|
|
"node": "core",
|
|
"port": "cmd_arg_i",
|
|
"expression": "s_cmd_arg"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "core.p2",
|
|
"to": "reg.p2",
|
|
"kind": "data",
|
|
"label": "PIO RX / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/storage/apb4_sdio.sv",
|
|
"text": ".pio_rdata_o(s_pio_rdata)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/storage/apb4_sdio.sv",
|
|
"text": ".pio_rdata_i(s_pio_rdata)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/storage/apb4_sdio.sv",
|
|
"scope": "apb4_sdio",
|
|
"symbol": "s_pio_rdata",
|
|
"bits": 32
|
|
},
|
|
{
|
|
"file": "rtl/ip/storage/apb4_sdio.sv",
|
|
"scope": "apb4_sdio",
|
|
"symbol": "s_pio_rdata",
|
|
"bits": 32
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "pio_rdata_o",
|
|
"expression": "s_pio_rdata"
|
|
},
|
|
{
|
|
"node": "reg",
|
|
"port": "pio_rdata_i",
|
|
"expression": "s_pio_rdata"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "core.p3",
|
|
"to": "memory.p3",
|
|
"kind": "data",
|
|
"label": "AXI4 / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/storage/apb4_sdio.sv",
|
|
"text": ".dma_axi4(dma_axi4)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "dma_axi4",
|
|
"expression": "dma_axi4"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "core.p4",
|
|
"to": "pads.p4",
|
|
"kind": "data",
|
|
"label": "SD signals",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/storage/apb4_sdio.sv",
|
|
"text": "assign sdio.dat_do_o = u_sdio_core_if.dat_do_o;"
|
|
},
|
|
{
|
|
"file": "rtl/ip/storage/apb4_sdio.sv",
|
|
"text": ".sdio(u_sdio_core_if)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "sdio",
|
|
"expression": "u_sdio_core_if"
|
|
}
|
|
]
|
|
}
|
|
],
|
|
"note": "Selected controller paths. Descriptor, byte-lane and command ordering are separate formats. SDIO1 keeps its own base, pads and IRQ; the protocol and descriptor formats are shared."
|
|
},
|
|
"psram": {
|
|
"nodes": [
|
|
{
|
|
"id": "reg",
|
|
"title": "APB4 configuration\ninitialization / status",
|
|
"x": 0.0,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/memory/apb4_psram.sv",
|
|
"rtl/ip/memory/psram_reg.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/memory/apb4_psram.sv",
|
|
"name": "u_psram_reg",
|
|
"module": "psram_reg",
|
|
"declaration_file": "rtl/ip/memory/psram_reg.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "axi",
|
|
"title": "AXI memory adapter\nrange / burst handling",
|
|
"x": 0.0,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p1",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "east"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/memory/apb4_psram.sv",
|
|
"rtl/ip/memory/psram_axi4.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/memory/apb4_psram.sv",
|
|
"name": "u_psram_axi4",
|
|
"module": "psram_axi4",
|
|
"declaration_file": "rtl/ip/memory/psram_axi4.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "core",
|
|
"title": "Memory controller\ninitialization / arbitration",
|
|
"x": 6.3,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p3",
|
|
"direction": "out",
|
|
"width": 64,
|
|
"side": "east"
|
|
},
|
|
{
|
|
"id": "p4",
|
|
"direction": "in",
|
|
"width": 256,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/memory/apb4_psram.sv",
|
|
"rtl/ip/memory/psram_core.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/memory/apb4_psram.sv",
|
|
"name": "u_psram_core",
|
|
"module": "psram_core",
|
|
"declaration_file": "rtl/ip/memory/psram_core.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "phy",
|
|
"title": "QPI PHY\nserial transfer engine",
|
|
"x": 12.6,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p3",
|
|
"direction": "in",
|
|
"width": 64,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p4",
|
|
"direction": "out",
|
|
"width": 256,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p5",
|
|
"direction": "out",
|
|
"width": 4,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/memory/apb4_psram.sv",
|
|
"rtl/ip/memory/psram_phy.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/memory/apb4_psram.sv",
|
|
"name": "u_psram_phy",
|
|
"module": "psram_phy",
|
|
"declaration_file": "rtl/ip/memory/psram_phy.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "pads",
|
|
"title": "Memory pads\nclock / CS / data",
|
|
"x": 12.6,
|
|
"y": 0.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p5",
|
|
"direction": "in",
|
|
"width": 4,
|
|
"side": "north"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/memory/apb4_psram.sv"
|
|
]
|
|
}
|
|
],
|
|
"edges": [
|
|
{
|
|
"from": "reg.p0",
|
|
"to": "core.p0",
|
|
"kind": "control",
|
|
"label": "ENABLE",
|
|
"style": "zigzag",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/memory/apb4_psram.sv",
|
|
"text": ".controller_enable_o(s_controller_en)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/memory/apb4_psram.sv",
|
|
"text": ".controller_enable_i(s_controller_en)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/memory/apb4_psram.sv",
|
|
"scope": "apb4_psram",
|
|
"symbol": "s_controller_en",
|
|
"bits": 1
|
|
},
|
|
{
|
|
"file": "rtl/ip/memory/apb4_psram.sv",
|
|
"scope": "apb4_psram",
|
|
"symbol": "s_controller_en",
|
|
"bits": 1
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "controller_enable_o",
|
|
"expression": "s_controller_en"
|
|
},
|
|
{
|
|
"node": "core",
|
|
"port": "controller_enable_i",
|
|
"expression": "s_controller_en"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "axi.p1",
|
|
"to": "core.p1",
|
|
"kind": "data",
|
|
"label": "WRITE / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/memory/apb4_psram.sv",
|
|
"text": ".mem_req_wdata_o(s_mem_req_wdata)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/memory/apb4_psram.sv",
|
|
"text": ".mem_req_wdata_i(s_mem_req_wdata)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/memory/apb4_psram.sv",
|
|
"scope": "apb4_psram",
|
|
"symbol": "s_mem_req_wdata",
|
|
"bits": 32
|
|
},
|
|
{
|
|
"file": "rtl/ip/memory/apb4_psram.sv",
|
|
"scope": "apb4_psram",
|
|
"symbol": "s_mem_req_wdata",
|
|
"bits": 32
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "axi",
|
|
"port": "mem_req_wdata_o",
|
|
"expression": "s_mem_req_wdata"
|
|
},
|
|
{
|
|
"node": "core",
|
|
"port": "mem_req_wdata_i",
|
|
"expression": "s_mem_req_wdata"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "core.p2",
|
|
"to": "axi.p2",
|
|
"kind": "data",
|
|
"label": "READ / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/memory/apb4_psram.sv",
|
|
"text": ".mem_rsp_rdata_o(s_mem_rsp_rdata)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/memory/apb4_psram.sv",
|
|
"text": ".mem_rsp_rdata_i(s_mem_rsp_rdata)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/memory/apb4_psram.sv",
|
|
"scope": "apb4_psram",
|
|
"symbol": "s_mem_rsp_rdata",
|
|
"bits": 32
|
|
},
|
|
{
|
|
"file": "rtl/ip/memory/apb4_psram.sv",
|
|
"scope": "apb4_psram",
|
|
"symbol": "s_mem_rsp_rdata",
|
|
"bits": 32
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "mem_rsp_rdata_o",
|
|
"expression": "s_mem_rsp_rdata"
|
|
},
|
|
{
|
|
"node": "axi",
|
|
"port": "mem_rsp_rdata_i",
|
|
"expression": "s_mem_rsp_rdata"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "core.p3",
|
|
"to": "phy.p3",
|
|
"kind": "data",
|
|
"label": "WRITE / 64",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/memory/apb4_psram.sv",
|
|
"text": ".phy_req_wdata_o(s_phy_req_wdata)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/memory/apb4_psram.sv",
|
|
"text": ".req_wdata_i(s_phy_req_wdata)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/memory/apb4_psram.sv",
|
|
"scope": "apb4_psram",
|
|
"symbol": "s_phy_req_wdata",
|
|
"bits": 64
|
|
},
|
|
{
|
|
"file": "rtl/ip/memory/apb4_psram.sv",
|
|
"scope": "apb4_psram",
|
|
"symbol": "s_phy_req_wdata",
|
|
"bits": 64
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "phy_req_wdata_o",
|
|
"expression": "s_phy_req_wdata"
|
|
},
|
|
{
|
|
"node": "phy",
|
|
"port": "req_wdata_i",
|
|
"expression": "s_phy_req_wdata"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "phy.p4",
|
|
"to": "core.p4",
|
|
"kind": "data",
|
|
"label": "READ / 256",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/memory/apb4_psram.sv",
|
|
"text": ".rdata_o(s_phy_rdata)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/memory/apb4_psram.sv",
|
|
"text": ".phy_rdata_i(s_phy_rdata)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/memory/apb4_psram.sv",
|
|
"scope": "apb4_psram",
|
|
"symbol": "s_phy_rdata",
|
|
"bits": 256
|
|
},
|
|
{
|
|
"file": "rtl/ip/memory/apb4_psram.sv",
|
|
"scope": "apb4_psram",
|
|
"symbol": "s_phy_rdata",
|
|
"bits": 256
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "phy",
|
|
"port": "rdata_o",
|
|
"expression": "s_phy_rdata"
|
|
},
|
|
{
|
|
"node": "core",
|
|
"port": "phy_rdata_i",
|
|
"expression": "s_phy_rdata"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "phy.p5",
|
|
"to": "pads.p5",
|
|
"kind": "data",
|
|
"label": "DQ / 4",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/memory/apb4_psram.sv",
|
|
"text": ".psram_io_do_o(psram.io_do_o)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "phy",
|
|
"port": "psram_io_do_o",
|
|
"expression": "psram.io_do_o"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
}
|
|
],
|
|
"note": "Memory data and control are separate paths. Device capacity, readiness and protocol profile remain configuration-dependent. QPI framing and chip selection follow the current PHY and device profile."
|
|
},
|
|
"opipsram": {
|
|
"nodes": [
|
|
{
|
|
"id": "reg",
|
|
"title": "APB4 configuration\ninitialization / status",
|
|
"x": 0.0,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/memory/apb4_opipsram.sv",
|
|
"rtl/ip/memory/opipsram_reg.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/memory/apb4_opipsram.sv",
|
|
"name": "u_opipsram_reg",
|
|
"module": "opipsram_reg",
|
|
"declaration_file": "rtl/ip/memory/opipsram_reg.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "axi",
|
|
"title": "AXI memory adapter\nrange / burst handling",
|
|
"x": 0.0,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p1",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "east"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/memory/apb4_opipsram.sv",
|
|
"rtl/ip/memory/opipsram_axi4.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/memory/apb4_opipsram.sv",
|
|
"name": "u_opipsram_axi4",
|
|
"module": "opipsram_axi4",
|
|
"declaration_file": "rtl/ip/memory/opipsram_axi4.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "core",
|
|
"title": "Memory controller\ninitialization / arbitration",
|
|
"x": 6.3,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p3",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p7",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/memory/apb4_opipsram.sv",
|
|
"rtl/ip/memory/opipsram_core.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/memory/apb4_opipsram.sv",
|
|
"name": "u_opipsram_core",
|
|
"module": "opipsram_core",
|
|
"declaration_file": "rtl/ip/memory/opipsram_core.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "phy",
|
|
"title": "OPI / HyperBus PHY\nserial transfer engine",
|
|
"x": 12.6,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p4",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p5",
|
|
"direction": "out",
|
|
"width": 8,
|
|
"side": "south"
|
|
},
|
|
{
|
|
"id": "p6",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/memory/apb4_opipsram.sv",
|
|
"rtl/ip/memory/opipsram_phy.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/memory/apb4_opipsram.sv",
|
|
"name": "u_opipsram_phy",
|
|
"module": "opipsram_phy",
|
|
"declaration_file": "rtl/ip/memory/opipsram_phy.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "pads",
|
|
"title": "Memory pads\nclock / CS / data",
|
|
"x": 12.6,
|
|
"y": 0.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p5",
|
|
"direction": "in",
|
|
"width": 8,
|
|
"side": "north"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/memory/apb4_opipsram.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "cdc",
|
|
"title": "Command CDC\nrequest / acknowledge",
|
|
"x": 6.3,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p3",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "south"
|
|
},
|
|
{
|
|
"id": "p4",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/memory/apb4_opipsram.sv",
|
|
"rtl/managed/clusterip/common/rtl/cdc/cdc_2phase.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/memory/apb4_opipsram.sv",
|
|
"name": "u_command_cdc",
|
|
"module": "cdc_2phase",
|
|
"declaration_file": "rtl/managed/clusterip/common/rtl/cdc/cdc_2phase.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "response",
|
|
"title": "Response CDC\nrequest / acknowledge",
|
|
"x": 6.3,
|
|
"y": 0.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p6",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p7",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "north"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/memory/apb4_opipsram.sv",
|
|
"rtl/managed/clusterip/common/rtl/cdc/cdc_2phase.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/memory/apb4_opipsram.sv",
|
|
"name": "u_response_cdc",
|
|
"module": "cdc_2phase",
|
|
"declaration_file": "rtl/managed/clusterip/common/rtl/cdc/cdc_2phase.sv"
|
|
}
|
|
}
|
|
],
|
|
"edges": [
|
|
{
|
|
"from": "reg.p0",
|
|
"to": "core.p0",
|
|
"kind": "control",
|
|
"label": "ENABLE",
|
|
"style": "zigzag",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/memory/apb4_opipsram.sv",
|
|
"text": ".controller_enable_o(s_ctrl_en)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/memory/apb4_opipsram.sv",
|
|
"text": ".controller_enable_i(s_ctrl_en)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/memory/apb4_opipsram.sv",
|
|
"scope": "apb4_opipsram",
|
|
"symbol": "s_ctrl_en",
|
|
"bits": 1
|
|
},
|
|
{
|
|
"file": "rtl/ip/memory/apb4_opipsram.sv",
|
|
"scope": "apb4_opipsram",
|
|
"symbol": "s_ctrl_en",
|
|
"bits": 1
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "controller_enable_o",
|
|
"expression": "s_ctrl_en"
|
|
},
|
|
{
|
|
"node": "core",
|
|
"port": "controller_enable_i",
|
|
"expression": "s_ctrl_en"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "axi.p1",
|
|
"to": "core.p1",
|
|
"kind": "data",
|
|
"label": "WRITE / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/memory/apb4_opipsram.sv",
|
|
"text": ".core_req_wdata_o(s_mem_req_wdata)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/memory/apb4_opipsram.sv",
|
|
"text": ".mem_req_wdata_i(s_mem_req_wdata)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/memory/apb4_opipsram.sv",
|
|
"scope": "apb4_opipsram",
|
|
"symbol": "s_mem_req_wdata",
|
|
"bits": 32
|
|
},
|
|
{
|
|
"file": "rtl/ip/memory/apb4_opipsram.sv",
|
|
"scope": "apb4_opipsram",
|
|
"symbol": "s_mem_req_wdata",
|
|
"bits": 32
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "axi",
|
|
"port": "core_req_wdata_o",
|
|
"expression": "s_mem_req_wdata"
|
|
},
|
|
{
|
|
"node": "core",
|
|
"port": "mem_req_wdata_i",
|
|
"expression": "s_mem_req_wdata"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "core.p2",
|
|
"to": "axi.p2",
|
|
"kind": "data",
|
|
"label": "READ / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/memory/apb4_opipsram.sv",
|
|
"text": ".mem_rsp_rdata_o(s_mem_rsp_rdata)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/memory/apb4_opipsram.sv",
|
|
"text": ".core_rsp_rdata_i(s_mem_rsp_rdata)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/memory/apb4_opipsram.sv",
|
|
"scope": "apb4_opipsram",
|
|
"symbol": "s_mem_rsp_rdata",
|
|
"bits": 32
|
|
},
|
|
{
|
|
"file": "rtl/ip/memory/apb4_opipsram.sv",
|
|
"scope": "apb4_opipsram",
|
|
"symbol": "s_mem_rsp_rdata",
|
|
"bits": 32
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "mem_rsp_rdata_o",
|
|
"expression": "s_mem_rsp_rdata"
|
|
},
|
|
{
|
|
"node": "axi",
|
|
"port": "core_rsp_rdata_i",
|
|
"expression": "s_mem_rsp_rdata"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "core.p3",
|
|
"to": "cdc.p3",
|
|
"kind": "control",
|
|
"label": "CMD valid",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/memory/apb4_opipsram.sv",
|
|
"text": ".phy_req_valid_o(s_phy_req_valid)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/memory/apb4_opipsram.sv",
|
|
"text": ".src_valid_i(s_phy_req_valid)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/memory/apb4_opipsram.sv",
|
|
"scope": "apb4_opipsram",
|
|
"symbol": "s_phy_req_valid",
|
|
"bits": 1
|
|
},
|
|
{
|
|
"file": "rtl/ip/memory/apb4_opipsram.sv",
|
|
"scope": "apb4_opipsram",
|
|
"symbol": "s_phy_req_valid",
|
|
"bits": 1
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "phy_req_valid_o",
|
|
"expression": "s_phy_req_valid"
|
|
},
|
|
{
|
|
"node": "cdc",
|
|
"port": "src_valid_i",
|
|
"expression": "s_phy_req_valid"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "cdc.p4",
|
|
"to": "phy.p4",
|
|
"kind": "control",
|
|
"label": "CMD valid",
|
|
"style": "zigzag",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/memory/apb4_opipsram.sv",
|
|
"text": ".dst_valid_o(s_cmd_phy_valid)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/memory/apb4_opipsram.sv",
|
|
"text": ".cmd_valid_i(s_cmd_phy_valid)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/memory/apb4_opipsram.sv",
|
|
"scope": "apb4_opipsram",
|
|
"symbol": "s_cmd_phy_valid",
|
|
"bits": 1
|
|
},
|
|
{
|
|
"file": "rtl/ip/memory/apb4_opipsram.sv",
|
|
"scope": "apb4_opipsram",
|
|
"symbol": "s_cmd_phy_valid",
|
|
"bits": 1
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "cdc",
|
|
"port": "dst_valid_o",
|
|
"expression": "s_cmd_phy_valid"
|
|
},
|
|
{
|
|
"node": "phy",
|
|
"port": "cmd_valid_i",
|
|
"expression": "s_cmd_phy_valid"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "phy.p5",
|
|
"to": "pads.p5",
|
|
"kind": "data",
|
|
"label": "DQ / 8",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/memory/apb4_opipsram.sv",
|
|
"text": ".dq_o(psram.dq_o)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "phy",
|
|
"port": "dq_o",
|
|
"expression": "psram.dq_o"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "phy.p6",
|
|
"to": "response.p6",
|
|
"kind": "control",
|
|
"label": "RSP valid",
|
|
"style": "zigzag",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/memory/apb4_opipsram.sv",
|
|
"text": ".rsp_valid_o(s_rsp_phy_valid)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/memory/apb4_opipsram.sv",
|
|
"text": ".src_valid_i(s_rsp_phy_valid)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/memory/apb4_opipsram.sv",
|
|
"scope": "apb4_opipsram",
|
|
"symbol": "s_rsp_phy_valid",
|
|
"bits": 1
|
|
},
|
|
{
|
|
"file": "rtl/ip/memory/apb4_opipsram.sv",
|
|
"scope": "apb4_opipsram",
|
|
"symbol": "s_rsp_phy_valid",
|
|
"bits": 1
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "phy",
|
|
"port": "rsp_valid_o",
|
|
"expression": "s_rsp_phy_valid"
|
|
},
|
|
{
|
|
"node": "response",
|
|
"port": "src_valid_i",
|
|
"expression": "s_rsp_phy_valid"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "response.p7",
|
|
"to": "core.p7",
|
|
"kind": "control",
|
|
"label": "RSP valid",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/memory/apb4_opipsram.sv",
|
|
"text": ".dst_valid_o(s_rsp_sys_valid)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/memory/apb4_opipsram.sv",
|
|
"text": ".phy_rsp_valid_i(s_rsp_sys_valid)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/memory/apb4_opipsram.sv",
|
|
"scope": "apb4_opipsram",
|
|
"symbol": "s_rsp_sys_valid",
|
|
"bits": 1
|
|
},
|
|
{
|
|
"file": "rtl/ip/memory/apb4_opipsram.sv",
|
|
"scope": "apb4_opipsram",
|
|
"symbol": "s_rsp_sys_valid",
|
|
"bits": 1
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "response",
|
|
"port": "dst_valid_o",
|
|
"expression": "s_rsp_sys_valid"
|
|
},
|
|
{
|
|
"node": "core",
|
|
"port": "phy_rsp_valid_i",
|
|
"expression": "s_rsp_sys_valid"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
}
|
|
],
|
|
"note": "Memory data and control are separate paths. Device capacity, readiness and protocol profile remain configuration-dependent. Command and response bundles cross the PHY clock boundary through separate CDC handshakes."
|
|
},
|
|
"sdram": {
|
|
"nodes": [
|
|
{
|
|
"id": "reg",
|
|
"title": "APB4 registers\ntiming / initialization",
|
|
"x": 0.0,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/memory/axi4_sdram.sv",
|
|
"rtl/ip/memory/sdram_reg.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/memory/axi4_sdram.sv",
|
|
"name": "u_sdram_reg",
|
|
"module": "sdram_reg",
|
|
"declaration_file": "rtl/ip/memory/sdram_reg.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "axi",
|
|
"title": "AXI4 adapter\nread / write queues",
|
|
"x": 0.0,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p1",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "east"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/memory/axi4_sdram.sv",
|
|
"rtl/ip/memory/sdram_axi4.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/memory/axi4_sdram.sv",
|
|
"name": "u_sdram_axi4",
|
|
"module": "sdram_axi4",
|
|
"declaration_file": "rtl/ip/memory/sdram_axi4.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "core",
|
|
"title": "SDRAM core\nbank / row / refresh",
|
|
"x": 6.3,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p3",
|
|
"direction": "out",
|
|
"width": null,
|
|
"side": "east",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/memory/axi4_sdram.sv",
|
|
"rtl/ip/memory/sdram_core.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/memory/axi4_sdram.sv",
|
|
"name": "u_sdram_core",
|
|
"module": "sdram_core",
|
|
"declaration_file": "rtl/ip/memory/sdram_core.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "pads",
|
|
"title": "SDRAM interface\naddress / command / DQ",
|
|
"x": 12.6,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p3",
|
|
"direction": "in",
|
|
"width": null,
|
|
"side": "west",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/memory/axi4_sdram.sv"
|
|
]
|
|
}
|
|
],
|
|
"edges": [
|
|
{
|
|
"from": "reg.p0",
|
|
"to": "core.p0",
|
|
"kind": "control",
|
|
"label": "INIT",
|
|
"style": "zigzag",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/memory/axi4_sdram.sv",
|
|
"text": ".init_start_o(s_init_start)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/memory/axi4_sdram.sv",
|
|
"text": ".init_start_i(s_init_start)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/memory/axi4_sdram.sv",
|
|
"scope": "axi4_sdram",
|
|
"symbol": "s_init_start",
|
|
"bits": 1
|
|
},
|
|
{
|
|
"file": "rtl/ip/memory/axi4_sdram.sv",
|
|
"scope": "axi4_sdram",
|
|
"symbol": "s_init_start",
|
|
"bits": 1
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "init_start_o",
|
|
"expression": "s_init_start"
|
|
},
|
|
{
|
|
"node": "core",
|
|
"port": "init_start_i",
|
|
"expression": "s_init_start"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "axi.p1",
|
|
"to": "core.p1",
|
|
"kind": "data",
|
|
"label": "WRITE / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/memory/axi4_sdram.sv",
|
|
"text": ".wr_data_wdata_o(s_wr_data_wdata)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/memory/axi4_sdram.sv",
|
|
"text": ".wr_data_wdata_i(s_wr_data_wdata)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/memory/axi4_sdram.sv",
|
|
"scope": "axi4_sdram",
|
|
"symbol": "s_wr_data_wdata",
|
|
"bits": 32
|
|
},
|
|
{
|
|
"file": "rtl/ip/memory/axi4_sdram.sv",
|
|
"scope": "axi4_sdram",
|
|
"symbol": "s_wr_data_wdata",
|
|
"bits": 32
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "axi",
|
|
"port": "wr_data_wdata_o",
|
|
"expression": "s_wr_data_wdata"
|
|
},
|
|
{
|
|
"node": "core",
|
|
"port": "wr_data_wdata_i",
|
|
"expression": "s_wr_data_wdata"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "core.p2",
|
|
"to": "axi.p2",
|
|
"kind": "data",
|
|
"label": "READ / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/memory/axi4_sdram.sv",
|
|
"text": ".rd_data_rdata_o(s_rd_data_rdata)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/memory/axi4_sdram.sv",
|
|
"text": ".rd_data_rdata_i(s_rd_data_rdata)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/memory/axi4_sdram.sv",
|
|
"scope": "axi4_sdram",
|
|
"symbol": "s_rd_data_rdata",
|
|
"bits": 32
|
|
},
|
|
{
|
|
"file": "rtl/ip/memory/axi4_sdram.sv",
|
|
"scope": "axi4_sdram",
|
|
"symbol": "s_rd_data_rdata",
|
|
"bits": 32
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "rd_data_rdata_o",
|
|
"expression": "s_rd_data_rdata"
|
|
},
|
|
{
|
|
"node": "axi",
|
|
"port": "rd_data_rdata_i",
|
|
"expression": "s_rd_data_rdata"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "core.p3",
|
|
"to": "pads.p3",
|
|
"kind": "data",
|
|
"label": "SDRAM",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/memory/axi4_sdram.sv",
|
|
"text": ".sdram(sdram)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "sdram",
|
|
"expression": "sdram"
|
|
}
|
|
]
|
|
}
|
|
],
|
|
"note": "The AXI adapter and SDRAM core use the configured word geometry. Initialization, refresh credits and programmed timing are controller policy, not board timing signoff."
|
|
},
|
|
"rtc": {
|
|
"nodes": [
|
|
{
|
|
"id": "apb",
|
|
"title": "APB4 interface\n32-bit register access",
|
|
"x": 0.0,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/managed/clusterip/rtc/rtl/apb4_rtc.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "reg",
|
|
"title": "APB register bank",
|
|
"x": 0.0,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "east"
|
|
},
|
|
{
|
|
"id": "p4",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/managed/clusterip/rtc/rtl/apb4_rtc.sv",
|
|
"rtl/managed/clusterip/rtc/rtl/rtc_reg.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/managed/clusterip/rtc/rtl/apb4_rtc.sv",
|
|
"name": "u_rtc_reg",
|
|
"module": "rtc_reg",
|
|
"declaration_file": "rtl/managed/clusterip/rtc/rtl/rtc_reg.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "request",
|
|
"title": "Command mailbox\nclock-domain crossing",
|
|
"x": 6.3,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p1",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/managed/clusterip/rtc/rtl/apb4_rtc.sv",
|
|
"rtl/managed/clusterip/common/rtl/cdc/async_reqack.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/managed/clusterip/rtc/rtl/apb4_rtc.sv",
|
|
"name": "u_command_mailbox",
|
|
"module": "async_reqack",
|
|
"declaration_file": "rtl/managed/clusterip/common/rtl/cdc/async_reqack.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "core",
|
|
"title": "RTC counter / calendar\nindependent clock domain",
|
|
"x": 12.6,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p2",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p3",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "south"
|
|
},
|
|
{
|
|
"id": "p5",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/managed/clusterip/rtc/rtl/apb4_rtc.sv",
|
|
"rtl/managed/clusterip/rtc/rtl/rtc_core.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/managed/clusterip/rtc/rtl/apb4_rtc.sv",
|
|
"name": "u_rtc_core",
|
|
"module": "rtc_core",
|
|
"declaration_file": "rtl/managed/clusterip/rtc/rtl/rtc_core.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "response",
|
|
"title": "Response mailbox\nclock-domain crossing",
|
|
"x": 6.3,
|
|
"y": 0.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p3",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p4",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "north"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/managed/clusterip/rtc/rtl/apb4_rtc.sv",
|
|
"rtl/managed/clusterip/common/rtl/cdc/async_reqack.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/managed/clusterip/rtc/rtl/apb4_rtc.sv",
|
|
"name": "u_response_mailbox",
|
|
"module": "async_reqack",
|
|
"declaration_file": "rtl/managed/clusterip/common/rtl/cdc/async_reqack.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "event",
|
|
"title": "Wake request",
|
|
"x": 12.6,
|
|
"y": 0.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p5",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "north"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/managed/clusterip/rtc/rtl/apb4_rtc.sv"
|
|
]
|
|
}
|
|
],
|
|
"edges": [
|
|
{
|
|
"from": "apb.p0",
|
|
"to": "reg.p0",
|
|
"kind": "control",
|
|
"label": "WRITE enable",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/managed/clusterip/rtc/rtl/apb4_rtc.sv",
|
|
"text": ".pwrite_i(apb4.pwrite)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "pwrite_i",
|
|
"expression": "apb4.pwrite"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "reg.p1",
|
|
"to": "request.p1",
|
|
"kind": "control",
|
|
"label": "CMD valid",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/managed/clusterip/rtc/rtl/apb4_rtc.sv",
|
|
"text": ".command_valid_o(s_command_valid_apb)"
|
|
},
|
|
{
|
|
"file": "rtl/managed/clusterip/rtc/rtl/apb4_rtc.sv",
|
|
"text": ".src_valid_i(s_command_valid_apb)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/managed/clusterip/rtc/rtl/apb4_rtc.sv",
|
|
"scope": "apb4_rtc",
|
|
"symbol": "s_command_valid_apb",
|
|
"bits": 1
|
|
},
|
|
{
|
|
"file": "rtl/managed/clusterip/rtc/rtl/apb4_rtc.sv",
|
|
"scope": "apb4_rtc",
|
|
"symbol": "s_command_valid_apb",
|
|
"bits": 1
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "command_valid_o",
|
|
"expression": "s_command_valid_apb"
|
|
},
|
|
{
|
|
"node": "request",
|
|
"port": "src_valid_i",
|
|
"expression": "s_command_valid_apb"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "request.p2",
|
|
"to": "core.p2",
|
|
"kind": "control",
|
|
"label": "CMD valid",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/managed/clusterip/rtc/rtl/apb4_rtc.sv",
|
|
"text": ".dst_valid_o(s_command_valid_rtc)"
|
|
},
|
|
{
|
|
"file": "rtl/managed/clusterip/rtc/rtl/apb4_rtc.sv",
|
|
"text": ".command_valid_i(s_command_valid_rtc)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/managed/clusterip/rtc/rtl/apb4_rtc.sv",
|
|
"scope": "apb4_rtc",
|
|
"symbol": "s_command_valid_rtc",
|
|
"bits": 1
|
|
},
|
|
{
|
|
"file": "rtl/managed/clusterip/rtc/rtl/apb4_rtc.sv",
|
|
"scope": "apb4_rtc",
|
|
"symbol": "s_command_valid_rtc",
|
|
"bits": 1
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "request",
|
|
"port": "dst_valid_o",
|
|
"expression": "s_command_valid_rtc"
|
|
},
|
|
{
|
|
"node": "core",
|
|
"port": "command_valid_i",
|
|
"expression": "s_command_valid_rtc"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "core.p3",
|
|
"to": "response.p3",
|
|
"kind": "control",
|
|
"label": "RSP valid",
|
|
"style": "zigzag",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/managed/clusterip/rtc/rtl/apb4_rtc.sv",
|
|
"text": ".response_valid_o(s_response_valid_rtc)"
|
|
},
|
|
{
|
|
"file": "rtl/managed/clusterip/rtc/rtl/apb4_rtc.sv",
|
|
"text": ".src_valid_i(s_response_valid_rtc)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/managed/clusterip/rtc/rtl/apb4_rtc.sv",
|
|
"scope": "apb4_rtc",
|
|
"symbol": "s_response_valid_rtc",
|
|
"bits": 1
|
|
},
|
|
{
|
|
"file": "rtl/managed/clusterip/rtc/rtl/apb4_rtc.sv",
|
|
"scope": "apb4_rtc",
|
|
"symbol": "s_response_valid_rtc",
|
|
"bits": 1
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "response_valid_o",
|
|
"expression": "s_response_valid_rtc"
|
|
},
|
|
{
|
|
"node": "response",
|
|
"port": "src_valid_i",
|
|
"expression": "s_response_valid_rtc"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "response.p4",
|
|
"to": "reg.p4",
|
|
"kind": "control",
|
|
"label": "RSP valid",
|
|
"style": "zigzag",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/managed/clusterip/rtc/rtl/apb4_rtc.sv",
|
|
"text": ".dst_valid_o(s_response_valid_apb)"
|
|
},
|
|
{
|
|
"file": "rtl/managed/clusterip/rtc/rtl/apb4_rtc.sv",
|
|
"text": ".response_valid_i(s_response_valid_apb)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/managed/clusterip/rtc/rtl/apb4_rtc.sv",
|
|
"scope": "apb4_rtc",
|
|
"symbol": "s_response_valid_apb",
|
|
"bits": 1
|
|
},
|
|
{
|
|
"file": "rtl/managed/clusterip/rtc/rtl/apb4_rtc.sv",
|
|
"scope": "apb4_rtc",
|
|
"symbol": "s_response_valid_apb",
|
|
"bits": 1
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "response",
|
|
"port": "dst_valid_o",
|
|
"expression": "s_response_valid_apb"
|
|
},
|
|
{
|
|
"node": "reg",
|
|
"port": "response_valid_i",
|
|
"expression": "s_response_valid_apb"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "core.p5",
|
|
"to": "event.p5",
|
|
"kind": "control",
|
|
"label": "WAKE",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/managed/clusterip/rtc/rtl/apb4_rtc.sv",
|
|
"text": ".wake_o(rtc.wake_o)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "wake_o",
|
|
"expression": "rtc.wake_o"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
}
|
|
],
|
|
"note": "Control requests and responses cross independent clock domains through explicit mailboxes. Status synchronizers are not command FIFOs; reset and retention rules remain those of the managed IP integration."
|
|
},
|
|
"wdg": {
|
|
"nodes": [
|
|
{
|
|
"id": "apb",
|
|
"title": "APB4 interface\n32-bit register access",
|
|
"x": 0.0,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/managed/clusterip/wdg/rtl/apb4_wdg.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "reg",
|
|
"title": "APB register bank",
|
|
"x": 0.0,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "east"
|
|
},
|
|
{
|
|
"id": "p4",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/managed/clusterip/wdg/rtl/apb4_wdg.sv",
|
|
"rtl/managed/clusterip/wdg/rtl/wdg_reg.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/managed/clusterip/wdg/rtl/apb4_wdg.sv",
|
|
"name": "u_wdg_reg",
|
|
"module": "wdg_reg",
|
|
"declaration_file": "rtl/managed/clusterip/wdg/rtl/wdg_reg.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "request",
|
|
"title": "Command mailbox\nclock-domain crossing",
|
|
"x": 6.3,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p1",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/managed/clusterip/wdg/rtl/apb4_wdg.sv",
|
|
"rtl/managed/clusterip/common/rtl/cdc/async_reqack.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/managed/clusterip/wdg/rtl/apb4_wdg.sv",
|
|
"name": "u_command_mailbox",
|
|
"module": "async_reqack",
|
|
"declaration_file": "rtl/managed/clusterip/common/rtl/cdc/async_reqack.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "core",
|
|
"title": "Watchdog window / counter\nindependent clock domain",
|
|
"x": 12.6,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p2",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p3",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "south"
|
|
},
|
|
{
|
|
"id": "p5",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/managed/clusterip/wdg/rtl/apb4_wdg.sv",
|
|
"rtl/managed/clusterip/wdg/rtl/wdg_core.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/managed/clusterip/wdg/rtl/apb4_wdg.sv",
|
|
"name": "u_wdg_core",
|
|
"module": "wdg_core",
|
|
"declaration_file": "rtl/managed/clusterip/wdg/rtl/wdg_core.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "response",
|
|
"title": "Response mailbox\nclock-domain crossing",
|
|
"x": 6.3,
|
|
"y": 0.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p3",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p4",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "north"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/managed/clusterip/wdg/rtl/apb4_wdg.sv",
|
|
"rtl/managed/clusterip/common/rtl/cdc/async_reqack.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/managed/clusterip/wdg/rtl/apb4_wdg.sv",
|
|
"name": "u_response_mailbox",
|
|
"module": "async_reqack",
|
|
"declaration_file": "rtl/managed/clusterip/common/rtl/cdc/async_reqack.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "event",
|
|
"title": "System reset request",
|
|
"x": 12.6,
|
|
"y": 0.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p5",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "north"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/managed/clusterip/wdg/rtl/apb4_wdg.sv"
|
|
]
|
|
}
|
|
],
|
|
"edges": [
|
|
{
|
|
"from": "apb.p0",
|
|
"to": "reg.p0",
|
|
"kind": "control",
|
|
"label": "WRITE enable",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/managed/clusterip/wdg/rtl/apb4_wdg.sv",
|
|
"text": ".pwrite_i(apb4.pwrite)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "pwrite_i",
|
|
"expression": "apb4.pwrite"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "reg.p1",
|
|
"to": "request.p1",
|
|
"kind": "control",
|
|
"label": "CMD valid",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/managed/clusterip/wdg/rtl/apb4_wdg.sv",
|
|
"text": ".command_valid_o(s_command_valid_apb)"
|
|
},
|
|
{
|
|
"file": "rtl/managed/clusterip/wdg/rtl/apb4_wdg.sv",
|
|
"text": ".src_valid_i(s_command_valid_apb)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/managed/clusterip/wdg/rtl/apb4_wdg.sv",
|
|
"scope": "apb4_wdg",
|
|
"symbol": "s_command_valid_apb",
|
|
"bits": 1
|
|
},
|
|
{
|
|
"file": "rtl/managed/clusterip/wdg/rtl/apb4_wdg.sv",
|
|
"scope": "apb4_wdg",
|
|
"symbol": "s_command_valid_apb",
|
|
"bits": 1
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "command_valid_o",
|
|
"expression": "s_command_valid_apb"
|
|
},
|
|
{
|
|
"node": "request",
|
|
"port": "src_valid_i",
|
|
"expression": "s_command_valid_apb"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "request.p2",
|
|
"to": "core.p2",
|
|
"kind": "control",
|
|
"label": "CMD valid",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/managed/clusterip/wdg/rtl/apb4_wdg.sv",
|
|
"text": ".dst_valid_o(s_command_valid_wdg)"
|
|
},
|
|
{
|
|
"file": "rtl/managed/clusterip/wdg/rtl/apb4_wdg.sv",
|
|
"text": ".command_valid_i(s_command_valid_wdg)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/managed/clusterip/wdg/rtl/apb4_wdg.sv",
|
|
"scope": "apb4_wdg",
|
|
"symbol": "s_command_valid_wdg",
|
|
"bits": 1
|
|
},
|
|
{
|
|
"file": "rtl/managed/clusterip/wdg/rtl/apb4_wdg.sv",
|
|
"scope": "apb4_wdg",
|
|
"symbol": "s_command_valid_wdg",
|
|
"bits": 1
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "request",
|
|
"port": "dst_valid_o",
|
|
"expression": "s_command_valid_wdg"
|
|
},
|
|
{
|
|
"node": "core",
|
|
"port": "command_valid_i",
|
|
"expression": "s_command_valid_wdg"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "core.p3",
|
|
"to": "response.p3",
|
|
"kind": "control",
|
|
"label": "RSP valid",
|
|
"style": "zigzag",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/managed/clusterip/wdg/rtl/apb4_wdg.sv",
|
|
"text": ".response_valid_o(s_response_valid_wdg)"
|
|
},
|
|
{
|
|
"file": "rtl/managed/clusterip/wdg/rtl/apb4_wdg.sv",
|
|
"text": ".src_valid_i(s_response_valid_wdg)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/managed/clusterip/wdg/rtl/apb4_wdg.sv",
|
|
"scope": "apb4_wdg",
|
|
"symbol": "s_response_valid_wdg",
|
|
"bits": 1
|
|
},
|
|
{
|
|
"file": "rtl/managed/clusterip/wdg/rtl/apb4_wdg.sv",
|
|
"scope": "apb4_wdg",
|
|
"symbol": "s_response_valid_wdg",
|
|
"bits": 1
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "response_valid_o",
|
|
"expression": "s_response_valid_wdg"
|
|
},
|
|
{
|
|
"node": "response",
|
|
"port": "src_valid_i",
|
|
"expression": "s_response_valid_wdg"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "response.p4",
|
|
"to": "reg.p4",
|
|
"kind": "control",
|
|
"label": "RSP valid",
|
|
"style": "zigzag",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/managed/clusterip/wdg/rtl/apb4_wdg.sv",
|
|
"text": ".dst_valid_o(s_response_valid_apb)"
|
|
},
|
|
{
|
|
"file": "rtl/managed/clusterip/wdg/rtl/apb4_wdg.sv",
|
|
"text": ".response_valid_i(s_response_valid_apb)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/managed/clusterip/wdg/rtl/apb4_wdg.sv",
|
|
"scope": "apb4_wdg",
|
|
"symbol": "s_response_valid_apb",
|
|
"bits": 1
|
|
},
|
|
{
|
|
"file": "rtl/managed/clusterip/wdg/rtl/apb4_wdg.sv",
|
|
"scope": "apb4_wdg",
|
|
"symbol": "s_response_valid_apb",
|
|
"bits": 1
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "response",
|
|
"port": "dst_valid_o",
|
|
"expression": "s_response_valid_apb"
|
|
},
|
|
{
|
|
"node": "reg",
|
|
"port": "response_valid_i",
|
|
"expression": "s_response_valid_apb"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "core.p5",
|
|
"to": "event.p5",
|
|
"kind": "control",
|
|
"label": "RESET request",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/managed/clusterip/wdg/rtl/apb4_wdg.sv",
|
|
"text": ".reset_req_o(wdg.reset_req_o)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "reset_req_o",
|
|
"expression": "wdg.reset_req_o"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
}
|
|
],
|
|
"note": "Control requests and responses cross independent clock domains through explicit mailboxes. Status synchronizers are not command FIFOs; reset and retention rules remain those of the managed IP integration."
|
|
},
|
|
"uart1": {
|
|
"nodes": [
|
|
{
|
|
"id": "apb",
|
|
"title": "APB4 interface\nUART1 register window",
|
|
"x": 0.0,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/serial/apb4_uart.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "reg",
|
|
"title": "UART register bank\nTX / RX FIFO storage",
|
|
"x": 6.3,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "out",
|
|
"width": 8,
|
|
"side": "east"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "in",
|
|
"width": 12,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/serial/apb4_uart.sv",
|
|
"rtl/ip/serial/uart_reg.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/serial/apb4_uart.sv",
|
|
"name": "u_uart_reg",
|
|
"module": "uart_reg",
|
|
"declaration_file": "rtl/ip/serial/uart_reg.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "core",
|
|
"title": "UART baud generator\nTX / RX engines",
|
|
"x": 12.6,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p1",
|
|
"direction": "in",
|
|
"width": 8,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "out",
|
|
"width": 12,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p3",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "south"
|
|
},
|
|
{
|
|
"id": "p4",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/serial/apb4_uart.sv",
|
|
"rtl/ip/serial/uart_core.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/serial/apb4_uart.sv",
|
|
"name": "u_uart_core",
|
|
"module": "uart_core",
|
|
"declaration_file": "rtl/ip/serial/uart_core.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "pads",
|
|
"title": "Dedicated console\nTX / RX pads",
|
|
"x": 12.6,
|
|
"y": 0.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p3",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p4",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "north"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/serial/apb4_uart.sv"
|
|
]
|
|
}
|
|
],
|
|
"edges": [
|
|
{
|
|
"from": "apb.p0",
|
|
"to": "reg.p0",
|
|
"kind": "data",
|
|
"label": "APB4 / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/serial/apb4_uart.sv",
|
|
"text": ".apb4(apb4)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "apb4",
|
|
"expression": "apb4"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "reg.p1",
|
|
"to": "core.p1",
|
|
"kind": "data",
|
|
"label": "TX / 8",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/serial/apb4_uart.sv",
|
|
"text": ".tx_data_o(s_tx_data)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/serial/apb4_uart.sv",
|
|
"text": ".tx_data_i(s_tx_data)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/serial/apb4_uart.sv",
|
|
"scope": "apb4_uart",
|
|
"symbol": "s_tx_data",
|
|
"bits": 8
|
|
},
|
|
{
|
|
"file": "rtl/ip/serial/apb4_uart.sv",
|
|
"scope": "apb4_uart",
|
|
"symbol": "s_tx_data",
|
|
"bits": 8
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "tx_data_o",
|
|
"expression": "s_tx_data"
|
|
},
|
|
{
|
|
"node": "core",
|
|
"port": "tx_data_i",
|
|
"expression": "s_tx_data"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "core.p2",
|
|
"to": "reg.p2",
|
|
"kind": "data",
|
|
"label": "RX / 12",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/serial/apb4_uart.sv",
|
|
"text": ".rx_data_o(s_rx_data)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/serial/apb4_uart.sv",
|
|
"text": ".rx_data_i(s_rx_data)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/serial/apb4_uart.sv",
|
|
"scope": "apb4_uart",
|
|
"symbol": "s_rx_data",
|
|
"bits": 12
|
|
},
|
|
{
|
|
"file": "rtl/ip/serial/apb4_uart.sv",
|
|
"scope": "apb4_uart",
|
|
"symbol": "s_rx_data",
|
|
"bits": 12
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "rx_data_o",
|
|
"expression": "s_rx_data"
|
|
},
|
|
{
|
|
"node": "reg",
|
|
"port": "rx_data_i",
|
|
"expression": "s_rx_data"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "core.p3",
|
|
"to": "pads.p3",
|
|
"kind": "data",
|
|
"label": "TX",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/serial/apb4_uart.sv",
|
|
"text": ".tx_o(s_tx)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/serial/apb4_uart.sv",
|
|
"scope": "apb4_uart",
|
|
"symbol": "s_tx",
|
|
"bits": 1
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "tx_o",
|
|
"expression": "s_tx"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "pads.p4",
|
|
"to": "core.p4",
|
|
"kind": "data",
|
|
"label": "RX",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/serial/apb4_uart.sv",
|
|
"text": ".rx_i(uart.rx_i)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "rx_i",
|
|
"expression": "uart.rx_i"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
}
|
|
],
|
|
"note": "UART1 is the HP console instance with dedicated TX/RX pads and an HP PLIC route. DMA pacing and RTS/CTS are not connected for this instance. FIFO geometry and serial formatting are shared with UART0."
|
|
},
|
|
"pwm": {
|
|
"nodes": [
|
|
{
|
|
"id": "apb",
|
|
"title": "APB4 register interface",
|
|
"x": 0.0,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "east"
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/managed/clusterip/pwm/rtl/apb4_pwm.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "reg",
|
|
"title": "PWM channel state\ncounters / comparators",
|
|
"x": 6.3,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "out",
|
|
"width": null,
|
|
"side": "east",
|
|
"bundle": true
|
|
},
|
|
{
|
|
"id": "p3",
|
|
"direction": "in",
|
|
"width": null,
|
|
"side": "east",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/managed/clusterip/pwm/rtl/apb4_pwm.sv",
|
|
"rtl/managed/clusterip/pwm/rtl/pwm_reg.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/managed/clusterip/pwm/rtl/apb4_pwm.sv",
|
|
"name": "u_pwm_reg",
|
|
"module": "pwm_reg",
|
|
"declaration_file": "rtl/managed/clusterip/pwm/rtl/pwm_reg.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "pads",
|
|
"title": "PWM output pairs\nfault / sync / capture",
|
|
"x": 12.6,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p2",
|
|
"direction": "in",
|
|
"width": null,
|
|
"side": "west",
|
|
"bundle": true
|
|
},
|
|
{
|
|
"id": "p3",
|
|
"direction": "out",
|
|
"width": null,
|
|
"side": "west",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/managed/clusterip/pwm/rtl/apb4_pwm.sv"
|
|
]
|
|
}
|
|
],
|
|
"edges": [
|
|
{
|
|
"from": "apb.p0",
|
|
"to": "reg.p0",
|
|
"kind": "control",
|
|
"label": "R/W",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/managed/clusterip/pwm/rtl/apb4_pwm.sv",
|
|
"text": ".pwrite_i(apb4.pwrite)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "pwrite_i",
|
|
"expression": "apb4.pwrite"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "reg.p1",
|
|
"to": "apb.p1",
|
|
"kind": "data",
|
|
"label": "RDATA / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/managed/clusterip/pwm/rtl/apb4_pwm.sv",
|
|
"text": ".prdata_o(apb4.prdata)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "prdata_o",
|
|
"expression": "apb4.prdata"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "reg.p2",
|
|
"to": "pads.p2",
|
|
"kind": "data",
|
|
"label": "PWM outputs",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/managed/clusterip/pwm/rtl/apb4_pwm.sv",
|
|
"text": ".pwm_o(pwm.pwm_o)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "pwm_o",
|
|
"expression": "pwm.pwm_o"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "pads.p3",
|
|
"to": "reg.p3",
|
|
"kind": "control",
|
|
"label": "FAULT inputs",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/managed/clusterip/pwm/rtl/apb4_pwm.sv",
|
|
"text": ".fault_i(pwm.fault_i)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "fault_i",
|
|
"expression": "pwm.fault_i"
|
|
}
|
|
]
|
|
}
|
|
],
|
|
"note": "The named register module also contains the functional datapath shown here; it is not a separate invented engine. Integration, reset and supported access rules remain those of the current managed source."
|
|
},
|
|
"ps2": {
|
|
"nodes": [
|
|
{
|
|
"id": "apb",
|
|
"title": "APB4 register interface",
|
|
"x": 0.0,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "east"
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/managed/clusterip/ps2/rtl/apb4_ps2.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "reg",
|
|
"title": "PS/2 receive state\nfilter / frame / FIFO",
|
|
"x": 6.3,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "east"
|
|
},
|
|
{
|
|
"id": "p3",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/managed/clusterip/ps2/rtl/apb4_ps2.sv",
|
|
"rtl/managed/clusterip/ps2/rtl/ps2_reg.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/managed/clusterip/ps2/rtl/apb4_ps2.sv",
|
|
"name": "u_ps2_reg",
|
|
"module": "ps2_reg",
|
|
"declaration_file": "rtl/managed/clusterip/ps2/rtl/ps2_reg.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "pads",
|
|
"title": "PS/2 clock / data\nGPIO alternate function",
|
|
"x": 12.6,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p2",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p3",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "west"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/managed/clusterip/ps2/rtl/apb4_ps2.sv"
|
|
]
|
|
}
|
|
],
|
|
"edges": [
|
|
{
|
|
"from": "apb.p0",
|
|
"to": "reg.p0",
|
|
"kind": "control",
|
|
"label": "R/W",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/managed/clusterip/ps2/rtl/apb4_ps2.sv",
|
|
"text": ".pwrite_i(apb4.pwrite)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "pwrite_i",
|
|
"expression": "apb4.pwrite"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "reg.p1",
|
|
"to": "apb.p1",
|
|
"kind": "data",
|
|
"label": "RDATA / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/managed/clusterip/ps2/rtl/apb4_ps2.sv",
|
|
"text": ".prdata_o(apb4.prdata)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "prdata_o",
|
|
"expression": "apb4.prdata"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "pads.p2",
|
|
"to": "reg.p2",
|
|
"kind": "data",
|
|
"label": "DATA",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/managed/clusterip/ps2/rtl/apb4_ps2.sv",
|
|
"text": ".ps2_dat_i(ps2.ps2_dat_i)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "ps2_dat_i",
|
|
"expression": "ps2.ps2_dat_i"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "reg.p3",
|
|
"to": "pads.p3",
|
|
"kind": "data",
|
|
"label": "DATA drive",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/managed/clusterip/ps2/rtl/apb4_ps2.sv",
|
|
"text": ".ps2_dat_o(ps2.ps2_dat_o)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "ps2_dat_o",
|
|
"expression": "ps2.ps2_dat_o"
|
|
}
|
|
]
|
|
}
|
|
],
|
|
"note": "The named register module also contains the functional datapath shown here; it is not a separate invented engine. Integration, reset and supported access rules remain those of the current managed source."
|
|
},
|
|
"crc": {
|
|
"nodes": [
|
|
{
|
|
"id": "apb",
|
|
"title": "APB4 register interface",
|
|
"x": 0.0,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "east"
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/managed/clusterip/crc/rtl/apb4_crc.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "reg",
|
|
"title": "CRC state / update\npolynomial datapath",
|
|
"x": 6.3,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/managed/clusterip/crc/rtl/apb4_crc.sv",
|
|
"rtl/managed/clusterip/crc/rtl/crc_reg.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/managed/clusterip/crc/rtl/apb4_crc.sv",
|
|
"name": "u_crc_reg",
|
|
"module": "crc_reg",
|
|
"declaration_file": "rtl/managed/clusterip/crc/rtl/crc_reg.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "words",
|
|
"title": "APB payload words\nsoftware-owned stream",
|
|
"x": 6.3,
|
|
"y": 0.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p2",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "north"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/managed/clusterip/crc/rtl/apb4_crc.sv"
|
|
]
|
|
}
|
|
],
|
|
"edges": [
|
|
{
|
|
"from": "apb.p0",
|
|
"to": "reg.p0",
|
|
"kind": "control",
|
|
"label": "R/W",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/managed/clusterip/crc/rtl/apb4_crc.sv",
|
|
"text": ".pwrite_i(apb4.pwrite)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "pwrite_i",
|
|
"expression": "apb4.pwrite"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "reg.p1",
|
|
"to": "apb.p1",
|
|
"kind": "data",
|
|
"label": "RDATA / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/managed/clusterip/crc/rtl/apb4_crc.sv",
|
|
"text": ".prdata_o(apb4.prdata)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "prdata_o",
|
|
"expression": "apb4.prdata"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "words.p2",
|
|
"to": "reg.p2",
|
|
"kind": "data",
|
|
"label": "WDATA / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/managed/clusterip/crc/rtl/apb4_crc.sv",
|
|
"text": ".pwdata_i(apb4.pwdata)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "pwdata_i",
|
|
"expression": "apb4.pwdata"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
}
|
|
],
|
|
"note": "The named register module also contains the functional datapath shown here; it is not a separate invented engine. Integration, reset and supported access rules remain those of the current managed source."
|
|
},
|
|
"rng": {
|
|
"nodes": [
|
|
{
|
|
"id": "apb",
|
|
"title": "APB4 register interface",
|
|
"x": 0.0,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "east"
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/managed/clusterip/rng/rtl/apb4_rng.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "reg",
|
|
"title": "Entropy conditioning\nhealth / output state",
|
|
"x": 6.3,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "east"
|
|
},
|
|
{
|
|
"id": "p3",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/managed/clusterip/rng/rtl/apb4_rng.sv",
|
|
"rtl/managed/clusterip/rng/rtl/rng_reg.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/managed/clusterip/rng/rtl/apb4_rng.sv",
|
|
"name": "u_rng_reg",
|
|
"module": "rng_reg",
|
|
"declaration_file": "rtl/managed/clusterip/rng/rtl/rng_reg.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "entropy",
|
|
"title": "Entropy provider\nqualification boundary",
|
|
"x": 12.6,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p2",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p3",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "west"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/managed/clusterip/rng/rtl/apb4_rng.sv"
|
|
]
|
|
}
|
|
],
|
|
"edges": [
|
|
{
|
|
"from": "apb.p0",
|
|
"to": "reg.p0",
|
|
"kind": "control",
|
|
"label": "R/W",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/managed/clusterip/rng/rtl/apb4_rng.sv",
|
|
"text": ".pwrite_i(apb4.pwrite)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "pwrite_i",
|
|
"expression": "apb4.pwrite"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "reg.p1",
|
|
"to": "apb.p1",
|
|
"kind": "data",
|
|
"label": "RDATA / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/managed/clusterip/rng/rtl/apb4_rng.sv",
|
|
"text": ".prdata_o(apb4.prdata)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "prdata_o",
|
|
"expression": "apb4.prdata"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "entropy.p2",
|
|
"to": "reg.p2",
|
|
"kind": "data",
|
|
"label": "DATA / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/managed/clusterip/rng/rtl/apb4_rng.sv",
|
|
"text": ".entropy_data_i(entropy_data_i)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/managed/clusterip/rng/rtl/apb4_rng.sv",
|
|
"scope": "apb4_rng",
|
|
"symbol": "entropy_data_i",
|
|
"bits": 32
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "entropy_data_i",
|
|
"expression": "entropy_data_i"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "reg.p3",
|
|
"to": "entropy.p3",
|
|
"kind": "control",
|
|
"label": "READY",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/managed/clusterip/rng/rtl/apb4_rng.sv",
|
|
"text": ".entropy_ready_o(entropy_ready_o)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/managed/clusterip/rng/rtl/apb4_rng.sv",
|
|
"scope": "apb4_rng",
|
|
"symbol": "entropy_ready_o",
|
|
"bits": 1
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "entropy_ready_o",
|
|
"expression": "entropy_ready_o"
|
|
}
|
|
]
|
|
}
|
|
],
|
|
"note": "The named register module also contains the functional datapath shown here; it is not a separate invented engine. Integration, reset and supported access rules remain those of the current managed source."
|
|
},
|
|
"archinfo": {
|
|
"nodes": [
|
|
{
|
|
"id": "apb",
|
|
"title": "APB4 register interface",
|
|
"x": 0.0,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "east"
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/managed/clusterip/archinfo/rtl/apb4_archinfo.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "reg",
|
|
"title": "Architecture constants\ndevice-ID read policy",
|
|
"x": 6.3,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "in",
|
|
"width": null,
|
|
"side": "east",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/managed/clusterip/archinfo/rtl/apb4_archinfo.sv",
|
|
"rtl/managed/clusterip/archinfo/rtl/archinfo_reg.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/managed/clusterip/archinfo/rtl/apb4_archinfo.sv",
|
|
"name": "u_archinfo_reg",
|
|
"module": "archinfo_reg",
|
|
"declaration_file": "rtl/managed/clusterip/archinfo/rtl/archinfo_reg.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "id",
|
|
"title": "Device-ID input\nvalid / read permission",
|
|
"x": 12.6,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p2",
|
|
"direction": "out",
|
|
"width": null,
|
|
"side": "west",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/managed/clusterip/archinfo/rtl/apb4_archinfo.sv"
|
|
]
|
|
}
|
|
],
|
|
"edges": [
|
|
{
|
|
"from": "apb.p0",
|
|
"to": "reg.p0",
|
|
"kind": "control",
|
|
"label": "R/W",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/managed/clusterip/archinfo/rtl/apb4_archinfo.sv",
|
|
"text": ".pwrite_i(apb4.pwrite)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "pwrite_i",
|
|
"expression": "apb4.pwrite"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "reg.p1",
|
|
"to": "apb.p1",
|
|
"kind": "data",
|
|
"label": "RDATA / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/managed/clusterip/archinfo/rtl/apb4_archinfo.sv",
|
|
"text": ".prdata_o(apb4.prdata)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "prdata_o",
|
|
"expression": "apb4.prdata"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "id.p2",
|
|
"to": "reg.p2",
|
|
"kind": "data",
|
|
"label": "DEVICE ID",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/managed/clusterip/archinfo/rtl/apb4_archinfo.sv",
|
|
"text": ".device_id_i(device_id_i)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "device_id_i",
|
|
"expression": "device_id_i"
|
|
}
|
|
]
|
|
}
|
|
],
|
|
"note": "The named register module also contains the functional datapath shown here; it is not a separate invented engine. Integration, reset and supported access rules remain those of the current managed source."
|
|
},
|
|
"crypto": {
|
|
"nodes": [
|
|
{
|
|
"id": "reg",
|
|
"title": "APB4 register logic\ncommand / key / operands",
|
|
"x": 6.3,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "south"
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "south"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/security/apb4_crypto.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "aes",
|
|
"title": "AES SRAM engine\nkey schedule / modes",
|
|
"x": 0.0,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p3",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "south"
|
|
},
|
|
{
|
|
"id": "p4",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/security/apb4_crypto.sv",
|
|
"rtl/ip/security/crypto_aes_sram_engine.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/security/apb4_crypto.sv",
|
|
"name": "u_aes",
|
|
"module": "crypto_aes_sram_engine",
|
|
"declaration_file": "rtl/ip/security/crypto_aes_sram_engine.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "sha",
|
|
"title": "SHA SRAM engine\nschedule / compression",
|
|
"x": 6.3,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p1",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p5",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/security/apb4_crypto.sv",
|
|
"rtl/ip/security/crypto_sha2_sram_engine.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/security/apb4_crypto.sv",
|
|
"name": "u_sha",
|
|
"module": "crypto_sha2_sram_engine",
|
|
"declaration_file": "rtl/ip/security/crypto_sha2_sram_engine.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "rsa",
|
|
"title": "RSA SRAM core\nprepare / exponentiation",
|
|
"x": 12.6,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p2",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p6",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/security/apb4_crypto.sv",
|
|
"rtl/ip/security/crypto_rsa_sram_core.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/security/apb4_crypto.sv",
|
|
"name": "u_rsa",
|
|
"module": "crypto_rsa_sram_core",
|
|
"declaration_file": "rtl/ip/security/crypto_rsa_sram_core.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "stream",
|
|
"title": "PIO / stream selection\ninput and result words",
|
|
"x": 0.0,
|
|
"y": 0.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p3",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p4",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "north"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/security/apb4_crypto.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "sha_words",
|
|
"title": "PIO / stream selection\nSHA payload words",
|
|
"x": 6.3,
|
|
"y": 0.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p5",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "north"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/security/apb4_crypto.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "rsa_words",
|
|
"title": "APB storage portals\nresult / progress status",
|
|
"x": 12.6,
|
|
"y": 0.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p6",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "north"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/security/apb4_crypto.sv"
|
|
]
|
|
}
|
|
],
|
|
"edges": [
|
|
{
|
|
"from": "reg.p0",
|
|
"to": "aes.p0",
|
|
"kind": "control",
|
|
"label": "START",
|
|
"style": "zigzag",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/security/apb4_crypto.sv",
|
|
"text": ".start_i(s_start[0])"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "aes",
|
|
"port": "start_i",
|
|
"expression": "s_start[0]"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "reg.p1",
|
|
"to": "sha.p1",
|
|
"kind": "control",
|
|
"label": "START",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/security/apb4_crypto.sv",
|
|
"text": ".start_i(s_start[1])"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "sha",
|
|
"port": "start_i",
|
|
"expression": "s_start[1]"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "reg.p2",
|
|
"to": "rsa.p2",
|
|
"kind": "control",
|
|
"label": "START",
|
|
"style": "zigzag",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/security/apb4_crypto.sv",
|
|
"text": ".start_i(s_start[2])"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "rsa",
|
|
"port": "start_i",
|
|
"expression": "s_start[2]"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "stream.p3",
|
|
"to": "aes.p3",
|
|
"kind": "data",
|
|
"label": "INPUT / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/security/apb4_crypto.sv",
|
|
"text": ".input_data_i(s_aes_dma_active ? crypto_in_axis.tdata : s_wdata)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "aes",
|
|
"port": "input_data_i",
|
|
"expression": "s_aes_dma_active ? crypto_in_axis.tdata : s_wdata"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "aes.p4",
|
|
"to": "stream.p4",
|
|
"kind": "data",
|
|
"label": "OUTPUT / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/security/apb4_crypto.sv",
|
|
"text": ".output_data_o(s_aes_output_data)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/security/apb4_crypto.sv",
|
|
"scope": "apb4_crypto",
|
|
"symbol": "s_aes_output_data",
|
|
"bits": 32
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "aes",
|
|
"port": "output_data_o",
|
|
"expression": "s_aes_output_data"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "sha_words.p5",
|
|
"to": "sha.p5",
|
|
"kind": "data",
|
|
"label": "INPUT / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/security/apb4_crypto.sv",
|
|
"text": ".input_data_i(s_sha_dma_active ? crypto_in_axis.tdata : s_wdata)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "sha",
|
|
"port": "input_data_i",
|
|
"expression": "s_sha_dma_active ? crypto_in_axis.tdata : s_wdata"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "rsa.p6",
|
|
"to": "rsa_words.p6",
|
|
"kind": "data",
|
|
"label": "PROGRESS / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/security/apb4_crypto.sv",
|
|
"text": ".progress_o(s_rsa_progress)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "rsa",
|
|
"port": "progress_o",
|
|
"expression": "s_rsa_progress"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
}
|
|
],
|
|
"note": "AES and SHA consume PIO or selected stream words. AES/SHA constants and work state plus RSA operands/results reside in the six private SRAM banks behind the wrapper's storage controller. The engines remain independently sequenced; no descriptor queue or readable secret-key aperture is implied."
|
|
},
|
|
"i2s": {
|
|
"nodes": [
|
|
{
|
|
"id": "reg",
|
|
"title": "APB4 registers\nPIO / stream selection",
|
|
"x": 0.0,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p3",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/serial/apb4_i2s.sv",
|
|
"rtl/ip/serial/i2s_reg.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/serial/apb4_i2s.sv",
|
|
"name": "u_i2s_reg",
|
|
"module": "i2s_reg",
|
|
"declaration_file": "rtl/ip/serial/i2s_reg.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "tx",
|
|
"title": "TX CDC FIFO\nsystem to audio",
|
|
"x": 6.3,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "south"
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/serial/apb4_i2s.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/serial/apb4_i2s.sv",
|
|
"name": "u_tx_cdc_fifo",
|
|
"module": "cdc_fifo_warm_flush"
|
|
}
|
|
},
|
|
{
|
|
"id": "rx",
|
|
"title": "RX CDC FIFO\naudio to system",
|
|
"x": 6.3,
|
|
"y": 0.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p2",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p3",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "north"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/serial/apb4_i2s.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/serial/apb4_i2s.sv",
|
|
"name": "u_rx_cdc_fifo",
|
|
"module": "cdc_fifo_warm_flush"
|
|
}
|
|
},
|
|
{
|
|
"id": "core",
|
|
"title": "Audio-clock engine\nslot / serial timing",
|
|
"x": 12.6,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p1",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "south"
|
|
},
|
|
{
|
|
"id": "p4",
|
|
"direction": "out",
|
|
"width": null,
|
|
"side": "south",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/serial/apb4_i2s.sv",
|
|
"rtl/ip/serial/i2s_core.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/serial/apb4_i2s.sv",
|
|
"name": "u_i2s_core",
|
|
"module": "i2s_core",
|
|
"declaration_file": "rtl/ip/serial/i2s_core.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "pads",
|
|
"title": "I2S pad interface\nMCLK / BCLK / LRCK / SD",
|
|
"x": 12.6,
|
|
"y": 0.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p4",
|
|
"direction": "in",
|
|
"width": null,
|
|
"side": "north",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/serial/apb4_i2s.sv"
|
|
]
|
|
}
|
|
],
|
|
"edges": [
|
|
{
|
|
"from": "reg.p0",
|
|
"to": "tx.p0",
|
|
"kind": "data",
|
|
"label": "TX / 32",
|
|
"style": "zigzag",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/serial/apb4_i2s.sv",
|
|
"text": "assign s_tx_src_data = s_stream_tx_en ? tx_axis.tdata : s_tx_pio_data;"
|
|
},
|
|
{
|
|
"file": "rtl/ip/serial/apb4_i2s.sv",
|
|
"text": ".src_data_i(s_tx_src_data)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/serial/apb4_i2s.sv",
|
|
"scope": "apb4_i2s",
|
|
"symbol": "s_tx_src_data",
|
|
"bits": 32
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "tx",
|
|
"port": "src_data_i",
|
|
"expression": "s_tx_src_data"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "tx.p1",
|
|
"to": "core.p1",
|
|
"kind": "data",
|
|
"label": "TX / 32",
|
|
"style": "zigzag",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/serial/apb4_i2s.sv",
|
|
"text": ".dst_data_o(s_tx_dst_data)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/serial/apb4_i2s.sv",
|
|
"text": ".tx_data_i(s_tx_dst_data)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/serial/apb4_i2s.sv",
|
|
"scope": "apb4_i2s",
|
|
"symbol": "s_tx_dst_data",
|
|
"bits": 32
|
|
},
|
|
{
|
|
"file": "rtl/ip/serial/apb4_i2s.sv",
|
|
"scope": "apb4_i2s",
|
|
"symbol": "s_tx_dst_data",
|
|
"bits": 32
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "tx",
|
|
"port": "dst_data_o",
|
|
"expression": "s_tx_dst_data"
|
|
},
|
|
{
|
|
"node": "core",
|
|
"port": "tx_data_i",
|
|
"expression": "s_tx_dst_data"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "core.p2",
|
|
"to": "rx.p2",
|
|
"kind": "data",
|
|
"label": "RX / 32",
|
|
"style": "zigzag",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/serial/apb4_i2s.sv",
|
|
"text": "assign s_rx_src_data = s_core_rx_data;"
|
|
},
|
|
{
|
|
"file": "rtl/ip/serial/apb4_i2s.sv",
|
|
"text": ".rx_data_o(s_core_rx_data)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/serial/apb4_i2s.sv",
|
|
"scope": "apb4_i2s",
|
|
"symbol": "s_core_rx_data",
|
|
"bits": 32
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "rx_data_o",
|
|
"expression": "s_core_rx_data"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "rx.p3",
|
|
"to": "reg.p3",
|
|
"kind": "data",
|
|
"label": "RX / 32",
|
|
"style": "zigzag",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/serial/apb4_i2s.sv",
|
|
"text": "assign s_rx_pop_data = s_rx_dst_data;"
|
|
},
|
|
{
|
|
"file": "rtl/ip/serial/apb4_i2s.sv",
|
|
"text": ".dst_data_o(s_rx_dst_data)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/serial/apb4_i2s.sv",
|
|
"text": ".rx_pop_data_i(s_rx_pop_data)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/serial/apb4_i2s.sv",
|
|
"scope": "apb4_i2s",
|
|
"symbol": "s_rx_dst_data",
|
|
"bits": 32
|
|
},
|
|
{
|
|
"file": "rtl/ip/serial/apb4_i2s.sv",
|
|
"scope": "apb4_i2s",
|
|
"symbol": "s_rx_pop_data",
|
|
"bits": 32
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "rx",
|
|
"port": "dst_data_o",
|
|
"expression": "s_rx_dst_data"
|
|
},
|
|
{
|
|
"node": "reg",
|
|
"port": "rx_pop_data_i",
|
|
"expression": "s_rx_pop_data"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "core.p4",
|
|
"to": "pads.p4",
|
|
"kind": "data",
|
|
"label": "Audio signals",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/serial/apb4_i2s.sv",
|
|
"text": ".i2s(i2s)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "i2s",
|
|
"expression": "i2s"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
}
|
|
],
|
|
"note": "TX/RX payloads cross the system/audio boundary through separate warm-flush CDC FIFOs. Configuration and flush commands have separate handshakes. PIO and stream selection share the same FIFO paths."
|
|
},
|
|
"sysctrl": {
|
|
"nodes": [
|
|
{
|
|
"id": "apb",
|
|
"title": "APB4 control\n32-bit register access",
|
|
"x": 0.0,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/peripheral/apb4_sysctrl.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "reg",
|
|
"title": "Register bank\nconfiguration / status",
|
|
"x": 0.0,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "east"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/peripheral/apb4_sysctrl.sv",
|
|
"rtl/ip/peripheral/sysctrl_reg.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/peripheral/apb4_sysctrl.sv",
|
|
"name": "u_sysctrl_reg",
|
|
"module": "sysctrl_reg",
|
|
"declaration_file": "rtl/ip/peripheral/sysctrl_reg.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "core",
|
|
"title": "System control state\nfault / lifecycle policy",
|
|
"x": 6.3,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p1",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p3",
|
|
"direction": "out",
|
|
"width": null,
|
|
"side": "north",
|
|
"bundle": true
|
|
},
|
|
{
|
|
"id": "p4",
|
|
"direction": "out",
|
|
"width": null,
|
|
"side": "east",
|
|
"bundle": true
|
|
},
|
|
{
|
|
"id": "p5",
|
|
"direction": "out",
|
|
"width": null,
|
|
"side": "south",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/peripheral/apb4_sysctrl.sv",
|
|
"rtl/ip/peripheral/sysctrl_core.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/peripheral/apb4_sysctrl.sv",
|
|
"name": "u_sysctrl_core",
|
|
"module": "sysctrl_core",
|
|
"declaration_file": "rtl/ip/peripheral/sysctrl_core.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "pll",
|
|
"title": "PLL control interface\ncapability-gated",
|
|
"x": 12.6,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p3",
|
|
"direction": "in",
|
|
"width": null,
|
|
"side": "south",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/peripheral/apb4_sysctrl.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "clock",
|
|
"title": "Clock control interface\nroot / divider policy",
|
|
"x": 12.6,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p4",
|
|
"direction": "in",
|
|
"width": null,
|
|
"side": "west",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/peripheral/apb4_sysctrl.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "system",
|
|
"title": "System status / control\nboot / test / faults",
|
|
"x": 6.3,
|
|
"y": 0.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p5",
|
|
"direction": "in",
|
|
"width": null,
|
|
"side": "north",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/peripheral/apb4_sysctrl.sv"
|
|
]
|
|
}
|
|
],
|
|
"edges": [
|
|
{
|
|
"from": "apb.p0",
|
|
"to": "reg.p0",
|
|
"kind": "data",
|
|
"label": "APB4 / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_sysctrl.sv",
|
|
"text": ".apb4(apb4)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "apb4",
|
|
"expression": "apb4"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "reg.p1",
|
|
"to": "core.p1",
|
|
"kind": "data",
|
|
"label": "WRITE / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_sysctrl.sv",
|
|
"text": ".write_data_o(s_write_data)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_sysctrl.sv",
|
|
"text": ".write_data_i(s_write_data)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_sysctrl.sv",
|
|
"scope": "apb4_sysctrl",
|
|
"symbol": "s_write_data",
|
|
"bits": 32
|
|
},
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_sysctrl.sv",
|
|
"scope": "apb4_sysctrl",
|
|
"symbol": "s_write_data",
|
|
"bits": 32
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "write_data_o",
|
|
"expression": "s_write_data"
|
|
},
|
|
{
|
|
"node": "core",
|
|
"port": "write_data_i",
|
|
"expression": "s_write_data"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "core.p2",
|
|
"to": "reg.p2",
|
|
"kind": "data",
|
|
"label": "READ / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_sysctrl.sv",
|
|
"text": ".read_data_o(s_read_data)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_sysctrl.sv",
|
|
"text": ".read_data_i(s_read_data)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_sysctrl.sv",
|
|
"scope": "apb4_sysctrl",
|
|
"symbol": "s_read_data",
|
|
"bits": 32
|
|
},
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_sysctrl.sv",
|
|
"scope": "apb4_sysctrl",
|
|
"symbol": "s_read_data",
|
|
"bits": 32
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "read_data_o",
|
|
"expression": "s_read_data"
|
|
},
|
|
{
|
|
"node": "reg",
|
|
"port": "read_data_i",
|
|
"expression": "s_read_data"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "core.p3",
|
|
"to": "pll.p3",
|
|
"kind": "control",
|
|
"label": "PLL controls",
|
|
"style": "zigzag",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_sysctrl.sv",
|
|
"text": ".pll_ctrl(pll_ctrl)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "pll_ctrl",
|
|
"expression": "pll_ctrl"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "core.p4",
|
|
"to": "clock.p4",
|
|
"kind": "control",
|
|
"label": "CLK control",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_sysctrl.sv",
|
|
"text": ".clock_ctrl(clock_ctrl)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "clock_ctrl",
|
|
"expression": "clock_ctrl"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "core.p5",
|
|
"to": "system.p5",
|
|
"kind": "control",
|
|
"label": "System bundle",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_sysctrl.sv",
|
|
"text": ".sysctrl(sysctrl)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "sysctrl",
|
|
"expression": "sysctrl"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
}
|
|
],
|
|
"note": "Selected implementation paths; unshown handshakes, reset and IRQ details remain in the interface contract."
|
|
},
|
|
"rcu": {
|
|
"nodes": [
|
|
{
|
|
"id": "ref",
|
|
"title": "REF24 / safe external\naudio clock inputs",
|
|
"x": 0.0,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/rcu.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "core",
|
|
"title": "Clock/reset subsystem\nroot selection / gating",
|
|
"x": 6.3,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "in",
|
|
"width": null,
|
|
"side": "east",
|
|
"bundle": true
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "south"
|
|
},
|
|
{
|
|
"id": "p3",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "south"
|
|
},
|
|
{
|
|
"id": "p4",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/rcu.sv",
|
|
"rtl/mini/top/soc_clock_reset_subsystem.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/mini/top/rcu.sv",
|
|
"name": "u_clock_reset_subsystem",
|
|
"module": "soc_clock_reset_subsystem",
|
|
"declaration_file": "rtl/mini/top/soc_clock_reset_subsystem.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "controls",
|
|
"title": "SYSCTRL interfaces\nPLL / clock policy",
|
|
"x": 12.6,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p1",
|
|
"direction": "out",
|
|
"width": null,
|
|
"side": "west",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/rcu.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "lp",
|
|
"title": "AON / LP / PCLK\nreset synchronizers",
|
|
"x": 0.0,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p2",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "north"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/rcu.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "hp",
|
|
"title": "HP root / core clock\nrelease and isolation",
|
|
"x": 6.3,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p3",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "north"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/rcu.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "memory",
|
|
"title": "Memory / audio domains\nindependent reset outputs",
|
|
"x": 12.6,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p4",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "north"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/rcu.sv"
|
|
]
|
|
}
|
|
],
|
|
"edges": [
|
|
{
|
|
"from": "ref.p0",
|
|
"to": "core.p0",
|
|
"kind": "control",
|
|
"label": "REF24",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/rcu.sv",
|
|
"text": ".ref24_clk_i(ref24_clk_i)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/mini/top/rcu.sv",
|
|
"scope": "rcu",
|
|
"symbol": "ref24_clk_i",
|
|
"bits": 1
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "ref24_clk_i",
|
|
"expression": "ref24_clk_i"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "controls.p1",
|
|
"to": "core.p1",
|
|
"kind": "control",
|
|
"label": "CLK control",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/rcu.sv",
|
|
"text": ".clock_ctrl(clock_ctrl)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "clock_ctrl",
|
|
"expression": "clock_ctrl"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "core.p2",
|
|
"to": "lp.p2",
|
|
"kind": "control",
|
|
"label": "LP clock",
|
|
"style": "zigzag",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/rcu.sv",
|
|
"text": ".lp_clk_o(sys_clk_o)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/mini/top/rcu.sv",
|
|
"scope": "rcu",
|
|
"symbol": "sys_clk_o",
|
|
"bits": 1
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "lp_clk_o",
|
|
"expression": "sys_clk_o"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "core.p3",
|
|
"to": "hp.p3",
|
|
"kind": "control",
|
|
"label": "HP clock",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/rcu.sv",
|
|
"text": ".hp_clk_o(hp_clk_o)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/mini/top/rcu.sv",
|
|
"scope": "rcu",
|
|
"symbol": "hp_clk_o",
|
|
"bits": 1
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "hp_clk_o",
|
|
"expression": "hp_clk_o"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "core.p4",
|
|
"to": "memory.p4",
|
|
"kind": "control",
|
|
"label": "MEM clock",
|
|
"style": "zigzag",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/rcu.sv",
|
|
"text": ".mem_clk_o(mem_clk_o)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/mini/top/rcu.sv",
|
|
"scope": "rcu",
|
|
"symbol": "mem_clk_o",
|
|
"bits": 1
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "mem_clk_o",
|
|
"expression": "mem_clk_o"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
}
|
|
],
|
|
"note": "The wrapper instantiates the clock/reset subsystem. Arrows show declared domain outputs and control interfaces; frequencies and reset roots follow the committed profile. PLL is absent from the IHP130 reference configuration."
|
|
},
|
|
"system-clocks": {
|
|
"nodes": [
|
|
{
|
|
"id": "ref",
|
|
"title": "REF24 / safe external\naudio clock inputs",
|
|
"x": 0.0,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/rcu.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "core",
|
|
"title": "Clock/reset subsystem\nroot selection / gating",
|
|
"x": 6.3,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "in",
|
|
"width": null,
|
|
"side": "east",
|
|
"bundle": true
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "south"
|
|
},
|
|
{
|
|
"id": "p3",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "south"
|
|
},
|
|
{
|
|
"id": "p4",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/rcu.sv",
|
|
"rtl/mini/top/soc_clock_reset_subsystem.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/mini/top/rcu.sv",
|
|
"name": "u_clock_reset_subsystem",
|
|
"module": "soc_clock_reset_subsystem",
|
|
"declaration_file": "rtl/mini/top/soc_clock_reset_subsystem.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "controls",
|
|
"title": "SYSCTRL interfaces\nPLL / clock policy",
|
|
"x": 12.6,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p1",
|
|
"direction": "out",
|
|
"width": null,
|
|
"side": "west",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/rcu.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "lp",
|
|
"title": "AON / LP / PCLK\nreset synchronizers",
|
|
"x": 0.0,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p2",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "north"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/rcu.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "hp",
|
|
"title": "HP root / core clock\nrelease and isolation",
|
|
"x": 6.3,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p3",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "north"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/rcu.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "memory",
|
|
"title": "Memory / audio domains\nindependent reset outputs",
|
|
"x": 12.6,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p4",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "north"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/rcu.sv"
|
|
]
|
|
}
|
|
],
|
|
"edges": [
|
|
{
|
|
"from": "ref.p0",
|
|
"to": "core.p0",
|
|
"kind": "control",
|
|
"label": "REF24",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/rcu.sv",
|
|
"text": ".ref24_clk_i(ref24_clk_i)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/mini/top/rcu.sv",
|
|
"scope": "rcu",
|
|
"symbol": "ref24_clk_i",
|
|
"bits": 1
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "ref24_clk_i",
|
|
"expression": "ref24_clk_i"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "controls.p1",
|
|
"to": "core.p1",
|
|
"kind": "control",
|
|
"label": "CLK control",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/rcu.sv",
|
|
"text": ".clock_ctrl(clock_ctrl)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "clock_ctrl",
|
|
"expression": "clock_ctrl"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "core.p2",
|
|
"to": "lp.p2",
|
|
"kind": "control",
|
|
"label": "LP clock",
|
|
"style": "zigzag",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/rcu.sv",
|
|
"text": ".lp_clk_o(sys_clk_o)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/mini/top/rcu.sv",
|
|
"scope": "rcu",
|
|
"symbol": "sys_clk_o",
|
|
"bits": 1
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "lp_clk_o",
|
|
"expression": "sys_clk_o"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "core.p3",
|
|
"to": "hp.p3",
|
|
"kind": "control",
|
|
"label": "HP clock",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/rcu.sv",
|
|
"text": ".hp_clk_o(hp_clk_o)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/mini/top/rcu.sv",
|
|
"scope": "rcu",
|
|
"symbol": "hp_clk_o",
|
|
"bits": 1
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "hp_clk_o",
|
|
"expression": "hp_clk_o"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "core.p4",
|
|
"to": "memory.p4",
|
|
"kind": "control",
|
|
"label": "MEM clock",
|
|
"style": "zigzag",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/rcu.sv",
|
|
"text": ".mem_clk_o(mem_clk_o)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/mini/top/rcu.sv",
|
|
"scope": "rcu",
|
|
"symbol": "mem_clk_o",
|
|
"bits": 1
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "mem_clk_o",
|
|
"expression": "mem_clk_o"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
}
|
|
],
|
|
"note": "The wrapper instantiates the clock/reset subsystem. Arrows show declared domain outputs and control interfaces; frequencies and reset roots follow the committed profile. PLL is absent from the IHP130 reference configuration. Pixel, ULPI and JTAG remain external clock domains and use their integration reset/CDC boundaries."
|
|
},
|
|
"clint": {
|
|
"nodes": [
|
|
{
|
|
"id": "apb",
|
|
"title": "APB4 control\n32-bit register access",
|
|
"x": 0.0,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/peripheral/apb4_clint.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "reg",
|
|
"title": "Register bank\nconfiguration / status",
|
|
"x": 0.0,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "out",
|
|
"width": 64,
|
|
"side": "east"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "in",
|
|
"width": 64,
|
|
"side": "east"
|
|
},
|
|
{
|
|
"id": "p5",
|
|
"direction": "out",
|
|
"width": null,
|
|
"side": "south",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/peripheral/apb4_clint.sv",
|
|
"rtl/ip/peripheral/clint_reg.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/peripheral/apb4_clint.sv",
|
|
"name": "u_clint_reg",
|
|
"module": "clint_reg",
|
|
"declaration_file": "rtl/ip/peripheral/clint_reg.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "core",
|
|
"title": "Time counter / comparator\nsoftware interrupt state",
|
|
"x": 6.3,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p1",
|
|
"direction": "in",
|
|
"width": 64,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "out",
|
|
"width": 64,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p3",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p4",
|
|
"direction": "out",
|
|
"width": null,
|
|
"side": "east",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/peripheral/apb4_clint.sv",
|
|
"rtl/ip/peripheral/clint_core.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/peripheral/apb4_clint.sv",
|
|
"name": "u_clint_core",
|
|
"module": "clint_core",
|
|
"declaration_file": "rtl/ip/peripheral/clint_core.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "tick",
|
|
"title": "Shared timebase tick",
|
|
"x": 6.3,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p3",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/peripheral/apb4_clint.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "irq",
|
|
"title": "LP timer/software IRQ",
|
|
"x": 12.6,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p4",
|
|
"direction": "in",
|
|
"width": null,
|
|
"side": "west",
|
|
"bundle": true
|
|
},
|
|
{
|
|
"id": "p5",
|
|
"direction": "in",
|
|
"width": null,
|
|
"side": "south",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/peripheral/apb4_clint.sv"
|
|
]
|
|
}
|
|
],
|
|
"edges": [
|
|
{
|
|
"from": "apb.p0",
|
|
"to": "reg.p0",
|
|
"kind": "data",
|
|
"label": "APB4 / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_clint.sv",
|
|
"text": ".apb4(apb4)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "apb4",
|
|
"expression": "apb4"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "reg.p1",
|
|
"to": "core.p1",
|
|
"kind": "data",
|
|
"label": "LOAD / 64",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_clint.sv",
|
|
"text": ".mtime_load_value_o(s_mtime_load_value)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_clint.sv",
|
|
"text": ".mtime_load_value_i(s_mtime_load_value)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_clint.sv",
|
|
"scope": "apb4_clint",
|
|
"symbol": "s_mtime_load_value",
|
|
"bits": 64
|
|
},
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_clint.sv",
|
|
"scope": "apb4_clint",
|
|
"symbol": "s_mtime_load_value",
|
|
"bits": 64
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "mtime_load_value_o",
|
|
"expression": "s_mtime_load_value"
|
|
},
|
|
{
|
|
"node": "core",
|
|
"port": "mtime_load_value_i",
|
|
"expression": "s_mtime_load_value"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "core.p2",
|
|
"to": "reg.p2",
|
|
"kind": "data",
|
|
"label": "TIME / 64",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_clint.sv",
|
|
"text": ".mtime_o(s_mtime)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_clint.sv",
|
|
"text": ".mtime_i(s_mtime)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_clint.sv",
|
|
"scope": "apb4_clint",
|
|
"symbol": "s_mtime",
|
|
"bits": 64
|
|
},
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_clint.sv",
|
|
"scope": "apb4_clint",
|
|
"symbol": "s_mtime",
|
|
"bits": 64
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "mtime_o",
|
|
"expression": "s_mtime"
|
|
},
|
|
{
|
|
"node": "reg",
|
|
"port": "mtime_i",
|
|
"expression": "s_mtime"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "tick.p3",
|
|
"to": "core.p3",
|
|
"kind": "control",
|
|
"label": "TICK",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_clint.sv",
|
|
"text": ".tick_i(timebase_tick_i)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_clint.sv",
|
|
"scope": "apb4_clint",
|
|
"symbol": "timebase_tick_i",
|
|
"bits": 1
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "tick_i",
|
|
"expression": "timebase_tick_i"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "core.p4",
|
|
"to": "irq.p4",
|
|
"kind": "control",
|
|
"label": "Timer IRQ",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_clint.sv",
|
|
"text": ".timer_irq_o(s_timer_irq)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "timer_irq_o",
|
|
"expression": "s_timer_irq"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "reg.p5",
|
|
"to": "irq.p5",
|
|
"kind": "control",
|
|
"label": "Software IRQ",
|
|
"style": "dodge",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_clint.sv",
|
|
"text": ".msip_o(s_msip)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "msip_o",
|
|
"expression": "s_msip"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal",
|
|
"dodge-y": 1.7,
|
|
"dodge-margins": [
|
|
0,
|
|
0
|
|
]
|
|
}
|
|
],
|
|
"note": "The LP CLINT and HP ACLINT share this RTL family but own separate register windows and interrupt routing. HP logical contexts are not additional physical harts."
|
|
},
|
|
"hp-aclint": {
|
|
"nodes": [
|
|
{
|
|
"id": "apb",
|
|
"title": "APB4 control\n32-bit register access",
|
|
"x": 0.0,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/peripheral/apb4_clint.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "reg",
|
|
"title": "Register bank\nconfiguration / status",
|
|
"x": 0.0,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "out",
|
|
"width": 64,
|
|
"side": "east"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "in",
|
|
"width": 64,
|
|
"side": "east"
|
|
},
|
|
{
|
|
"id": "p5",
|
|
"direction": "out",
|
|
"width": null,
|
|
"side": "south",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/peripheral/apb4_clint.sv",
|
|
"rtl/ip/peripheral/clint_reg.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/peripheral/apb4_clint.sv",
|
|
"name": "u_clint_reg",
|
|
"module": "clint_reg",
|
|
"declaration_file": "rtl/ip/peripheral/clint_reg.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "core",
|
|
"title": "Time counter / comparator\nsoftware interrupt state",
|
|
"x": 6.3,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p1",
|
|
"direction": "in",
|
|
"width": 64,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "out",
|
|
"width": 64,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p3",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p4",
|
|
"direction": "out",
|
|
"width": null,
|
|
"side": "east",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/peripheral/apb4_clint.sv",
|
|
"rtl/ip/peripheral/clint_core.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/peripheral/apb4_clint.sv",
|
|
"name": "u_clint_core",
|
|
"module": "clint_core",
|
|
"declaration_file": "rtl/ip/peripheral/clint_core.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "tick",
|
|
"title": "Shared timebase tick",
|
|
"x": 6.3,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p3",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/peripheral/apb4_clint.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "irq",
|
|
"title": "HP timer/software routes",
|
|
"x": 12.6,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p4",
|
|
"direction": "in",
|
|
"width": null,
|
|
"side": "west",
|
|
"bundle": true
|
|
},
|
|
{
|
|
"id": "p5",
|
|
"direction": "in",
|
|
"width": null,
|
|
"side": "south",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/peripheral/apb4_clint.sv"
|
|
]
|
|
}
|
|
],
|
|
"edges": [
|
|
{
|
|
"from": "apb.p0",
|
|
"to": "reg.p0",
|
|
"kind": "data",
|
|
"label": "APB4 / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_clint.sv",
|
|
"text": ".apb4(apb4)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "apb4",
|
|
"expression": "apb4"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "reg.p1",
|
|
"to": "core.p1",
|
|
"kind": "data",
|
|
"label": "LOAD / 64",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_clint.sv",
|
|
"text": ".mtime_load_value_o(s_mtime_load_value)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_clint.sv",
|
|
"text": ".mtime_load_value_i(s_mtime_load_value)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_clint.sv",
|
|
"scope": "apb4_clint",
|
|
"symbol": "s_mtime_load_value",
|
|
"bits": 64
|
|
},
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_clint.sv",
|
|
"scope": "apb4_clint",
|
|
"symbol": "s_mtime_load_value",
|
|
"bits": 64
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "mtime_load_value_o",
|
|
"expression": "s_mtime_load_value"
|
|
},
|
|
{
|
|
"node": "core",
|
|
"port": "mtime_load_value_i",
|
|
"expression": "s_mtime_load_value"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "core.p2",
|
|
"to": "reg.p2",
|
|
"kind": "data",
|
|
"label": "TIME / 64",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_clint.sv",
|
|
"text": ".mtime_o(s_mtime)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_clint.sv",
|
|
"text": ".mtime_i(s_mtime)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_clint.sv",
|
|
"scope": "apb4_clint",
|
|
"symbol": "s_mtime",
|
|
"bits": 64
|
|
},
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_clint.sv",
|
|
"scope": "apb4_clint",
|
|
"symbol": "s_mtime",
|
|
"bits": 64
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "mtime_o",
|
|
"expression": "s_mtime"
|
|
},
|
|
{
|
|
"node": "reg",
|
|
"port": "mtime_i",
|
|
"expression": "s_mtime"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "tick.p3",
|
|
"to": "core.p3",
|
|
"kind": "control",
|
|
"label": "TICK",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_clint.sv",
|
|
"text": ".tick_i(timebase_tick_i)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_clint.sv",
|
|
"scope": "apb4_clint",
|
|
"symbol": "timebase_tick_i",
|
|
"bits": 1
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "tick_i",
|
|
"expression": "timebase_tick_i"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "core.p4",
|
|
"to": "irq.p4",
|
|
"kind": "control",
|
|
"label": "Timer IRQ",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_clint.sv",
|
|
"text": ".timer_irq_o(s_timer_irq)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "timer_irq_o",
|
|
"expression": "s_timer_irq"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "reg.p5",
|
|
"to": "irq.p5",
|
|
"kind": "control",
|
|
"label": "Software IRQ",
|
|
"style": "dodge",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_clint.sv",
|
|
"text": ".msip_o(s_msip)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "msip_o",
|
|
"expression": "s_msip"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal",
|
|
"dodge-y": 1.7,
|
|
"dodge-margins": [
|
|
0,
|
|
0
|
|
]
|
|
}
|
|
],
|
|
"note": "The LP CLINT and HP ACLINT share this RTL family but own separate register windows and interrupt routing. HP logical contexts are not additional physical harts."
|
|
},
|
|
"hp-plic": {
|
|
"nodes": [
|
|
{
|
|
"id": "sources",
|
|
"title": "Peripheral IRQ sources\n32 source slots",
|
|
"x": 0.0,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/apb4_periph.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "plic",
|
|
"title": "Pending / priority / claim\n2 context arbiters",
|
|
"x": 6.3,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "out",
|
|
"width": 2,
|
|
"side": "east"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "north"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/apb4_periph.sv",
|
|
"rtl/ip/peripheral/apb4_plic.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/mini/top/apb4_periph.sv",
|
|
"name": "u_apb4_hp_plic",
|
|
"module": "apb4_plic",
|
|
"declaration_file": "rtl/ip/peripheral/apb4_plic.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "hp",
|
|
"title": "HP machine / supervisor\nexternal interrupt inputs",
|
|
"x": 12.6,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p1",
|
|
"direction": "in",
|
|
"width": 2,
|
|
"side": "west"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/apb4_periph.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "apb",
|
|
"title": "APB4 configuration\npriority / enable / threshold",
|
|
"x": 6.3,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p2",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/apb4_periph.sv"
|
|
]
|
|
}
|
|
],
|
|
"edges": [
|
|
{
|
|
"from": "sources.p0",
|
|
"to": "plic.p0",
|
|
"kind": "control",
|
|
"label": "IRQ / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/apb4_periph.sv",
|
|
"text": ".source_i(s_hp_plic_source)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/mini/top/apb4_periph.sv",
|
|
"scope": "apb4_periph",
|
|
"symbol": "s_hp_plic_source",
|
|
"bits": 32
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "plic",
|
|
"port": "source_i",
|
|
"expression": "s_hp_plic_source"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "plic.p1",
|
|
"to": "hp.p1",
|
|
"kind": "control",
|
|
"label": "CTX / 2",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/apb4_periph.sv",
|
|
"text": ".context_irq_o(s_hp_plic_context_irq)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/mini/top/apb4_periph.sv",
|
|
"scope": "apb4_periph",
|
|
"symbol": "s_hp_plic_context_irq",
|
|
"bits": 2
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "plic",
|
|
"port": "context_irq_o",
|
|
"expression": "s_hp_plic_context_irq"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "apb.p2",
|
|
"to": "plic.p2",
|
|
"kind": "data",
|
|
"label": "APB4 / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/apb4_periph.sv",
|
|
"text": ".apb4(u_hp_plic_apb4_if)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "plic",
|
|
"port": "apb4",
|
|
"expression": "u_hp_plic_apb4_if"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
}
|
|
],
|
|
"note": "32 source slots feed two logical HP interrupt contexts. Pending/claimed state, priority and thresholds are inside apb4_plic. This is the HP external-interrupt controller, not the LP IRQ route."
|
|
},
|
|
"hp-mailbox": {
|
|
"nodes": [
|
|
{
|
|
"id": "apb",
|
|
"title": "APB4 register accesses\nLP / HP software",
|
|
"x": 0.0,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "out",
|
|
"width": null,
|
|
"side": "east",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/peripheral/apb4_hp_mailbox.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "reg",
|
|
"title": "Command / event words\nsequence / doorbell state",
|
|
"x": 6.3,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "in",
|
|
"width": null,
|
|
"side": "west",
|
|
"bundle": true
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/peripheral/apb4_hp_mailbox.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "lp",
|
|
"title": "LP interrupt route",
|
|
"x": 12.6,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p1",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/peripheral/apb4_hp_mailbox.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "hp",
|
|
"title": "HP interrupt route",
|
|
"x": 12.6,
|
|
"y": 0.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p2",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "north"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/peripheral/apb4_hp_mailbox.sv"
|
|
]
|
|
}
|
|
],
|
|
"edges": [
|
|
{
|
|
"from": "apb.p0",
|
|
"to": "reg.p0",
|
|
"kind": "data",
|
|
"label": "APB R/W",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_hp_mailbox.sv",
|
|
"text": "assign s_req_accept = apb4.psel && apb4.penable && !s_ready_q;"
|
|
}
|
|
],
|
|
"instance_ports": []
|
|
},
|
|
{
|
|
"from": "reg.p1",
|
|
"to": "lp.p1",
|
|
"kind": "control",
|
|
"label": "LP IRQ",
|
|
"style": "zigzag",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_hp_mailbox.sv",
|
|
"text": "assign lp_irq_o = s_lp_intr_state_q && s_lp_intr_en_q;"
|
|
}
|
|
],
|
|
"instance_ports": [],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "reg.p2",
|
|
"to": "hp.p2",
|
|
"kind": "control",
|
|
"label": "HP IRQ",
|
|
"style": "zigzag",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/peripheral/apb4_hp_mailbox.sv",
|
|
"text": "assign hp_irq_o = s_hp_intr_state_q && s_hp_intr_en_q;"
|
|
}
|
|
],
|
|
"instance_ports": [],
|
|
"zigzag-dir": "horizontal"
|
|
}
|
|
],
|
|
"note": "Command, argument and sequence words are shared registers. Doorbells are interrupt state; this mailbox is not a FIFO and does not copy a shared-memory payload."
|
|
},
|
|
"resource": {
|
|
"nodes": [
|
|
{
|
|
"id": "apb",
|
|
"title": "APB4 resource registers",
|
|
"x": 0.0,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/apb4_system.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "core",
|
|
"title": "Resource ownership\nhandoff / reset policy",
|
|
"x": 6.3,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "in",
|
|
"width": 10,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "out",
|
|
"width": 20,
|
|
"side": "east"
|
|
},
|
|
{
|
|
"id": "p3",
|
|
"direction": "out",
|
|
"width": 10,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/apb4_system.sv",
|
|
"rtl/mini/top/resource_controller.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/mini/top/apb4_system.sv",
|
|
"name": "u_resource_controller",
|
|
"module": "resource_controller",
|
|
"declaration_file": "rtl/mini/top/resource_controller.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "resources",
|
|
"title": "Resource idle / block\nacknowledgement inputs",
|
|
"x": 0.0,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p1",
|
|
"direction": "out",
|
|
"width": 10,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/apb4_system.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "owners",
|
|
"title": "Owner / reset / quiesce\noutputs to owned IPs",
|
|
"x": 12.6,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p2",
|
|
"direction": "in",
|
|
"width": 20,
|
|
"side": "west"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/apb4_system.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "irq",
|
|
"title": "LP / HP IRQ steering",
|
|
"x": 6.3,
|
|
"y": 0.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p3",
|
|
"direction": "in",
|
|
"width": 10,
|
|
"side": "north"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/apb4_system.sv"
|
|
]
|
|
}
|
|
],
|
|
"edges": [
|
|
{
|
|
"from": "apb.p0",
|
|
"to": "core.p0",
|
|
"kind": "data",
|
|
"label": "APB4 / 32",
|
|
"style": "zigzag",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/apb4_system.sv",
|
|
"text": ".apb4(u_resource_ctrl_apb4_if)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "apb4",
|
|
"expression": "u_resource_ctrl_apb4_if"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "resources.p1",
|
|
"to": "core.p1",
|
|
"kind": "control",
|
|
"label": "IDLE / 10",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/apb4_system.sv",
|
|
"text": ".idle_i(resource_idle_i)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/mini/top/apb4_system.sv",
|
|
"scope": "apb4_system",
|
|
"symbol": "resource_idle_i",
|
|
"bits": 10
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "idle_i",
|
|
"expression": "resource_idle_i"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "core.p2",
|
|
"to": "owners.p2",
|
|
"kind": "control",
|
|
"label": "OWNER / 20",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/apb4_system.sv",
|
|
"text": ".owner_o(s_resource_owner)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/mini/top/apb4_system.sv",
|
|
"scope": "apb4_system",
|
|
"symbol": "s_resource_owner",
|
|
"bits": 20
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "owner_o",
|
|
"expression": "s_resource_owner"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "core.p3",
|
|
"to": "irq.p3",
|
|
"kind": "control",
|
|
"label": "LP IRQ / 10",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/apb4_system.sv",
|
|
"text": ".irq_lp_o(s_resource_irq_lp)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/mini/top/apb4_system.sv",
|
|
"scope": "apb4_system",
|
|
"symbol": "s_resource_irq_lp",
|
|
"bits": 10
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "irq_lp_o",
|
|
"expression": "s_resource_irq_lp"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
}
|
|
],
|
|
"note": "Ten resources retain independent owner/lock/quiesce/reset state. Resource 8 owns GA2D; resource 9 owns NPU and routes LP vector 33 / HP PLIC source 12. IRQ steering and cache handoff are control relationships, not a payload DMA path."
|
|
},
|
|
"monitor": {
|
|
"nodes": [
|
|
{
|
|
"id": "events",
|
|
"title": "Initiator / target\ntransfer event taps",
|
|
"x": 0.0,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "out",
|
|
"width": 10,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/soc_data_plane.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "core",
|
|
"title": "Fabric monitor\ncounters / first fault",
|
|
"x": 6.3,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "in",
|
|
"width": 10,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/soc_data_plane.sv",
|
|
"rtl/mini/top/fabric_monitor.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/mini/top/soc_data_plane.sv",
|
|
"name": "u_fabric_monitor",
|
|
"module": "fabric_monitor",
|
|
"declaration_file": "rtl/mini/top/fabric_monitor.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "apb",
|
|
"title": "APB4 observation\nsnapshot / counter reads",
|
|
"x": 12.6,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p2",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "west"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/soc_data_plane.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "fault",
|
|
"title": "Fault / recovery\nflush observations",
|
|
"x": 6.3,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p1",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/soc_data_plane.sv"
|
|
]
|
|
}
|
|
],
|
|
"edges": [
|
|
{
|
|
"from": "events.p0",
|
|
"to": "core.p0",
|
|
"kind": "control",
|
|
"label": "Accept / 10",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/soc_data_plane.sv",
|
|
"text": ".master_read_accept_i(s_monitor_master_read_accept)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/mini/top/soc_data_plane.sv",
|
|
"scope": "soc_data_plane",
|
|
"symbol": "s_monitor_master_read_accept",
|
|
"bits": 10
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "master_read_accept_i",
|
|
"expression": "s_monitor_master_read_accept"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "fault.p1",
|
|
"to": "core.p1",
|
|
"kind": "control",
|
|
"label": "FAULT valid",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/soc_data_plane.sv",
|
|
"text": ".fault_valid_i(fault_valid_o && fault_ready_i)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/mini/top/soc_data_plane.sv",
|
|
"scope": "soc_data_plane",
|
|
"symbol": "fault_valid_o",
|
|
"bits": 1
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "fault_valid_i",
|
|
"expression": "fault_valid_o && fault_ready_i"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "core.p2",
|
|
"to": "apb.p2",
|
|
"kind": "data",
|
|
"label": "APB4 / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/soc_data_plane.sv",
|
|
"text": ".apb4(fabric_monitor_apb4)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "apb4",
|
|
"expression": "fabric_monitor_apb4"
|
|
}
|
|
]
|
|
}
|
|
],
|
|
"note": "The monitor observes accepted transfers, outstanding work, stalls and fault records. It is not in the payload datapath. Arrays follow the configured initiator/target inventory."
|
|
},
|
|
"sram": {
|
|
"nodes": [
|
|
{
|
|
"id": "fabric",
|
|
"title": "HP-domain AXI64 fabric",
|
|
"x": 0.0,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "out",
|
|
"width": 64,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/retrosoc.sv",
|
|
"rtl/mini/top/soc_data_plane.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_data_plane",
|
|
"module": "soc_data_plane",
|
|
"declaration_file": "rtl/mini/top/soc_data_plane.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "ram",
|
|
"title": "On-chip SRAM target\naddress / bank / response",
|
|
"x": 6.3,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "in",
|
|
"width": 64,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "out",
|
|
"width": 64,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/retrosoc.sv",
|
|
"rtl/ip/memory/onchip_ram.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_onchip_ram",
|
|
"module": "onchip_ram",
|
|
"declaration_file": "rtl/ip/memory/onchip_ram.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "apb",
|
|
"title": "APB4 observation\nperformance counters",
|
|
"x": 6.3,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p1",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/retrosoc.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "banks",
|
|
"title": "IHP130 storage banks\n32 KiB configured capacity",
|
|
"x": 12.6,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p2",
|
|
"direction": "in",
|
|
"width": 64,
|
|
"side": "west"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/memory/onchip_ram.sv"
|
|
]
|
|
}
|
|
],
|
|
"edges": [
|
|
{
|
|
"from": "fabric.p0",
|
|
"to": "ram.p0",
|
|
"kind": "data",
|
|
"label": "AXI4 / 64",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"text": ".DataWidth(64)"
|
|
},
|
|
{
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"text": ".sram_gateway_axi4(u_data_sram_axi4_if)"
|
|
},
|
|
{
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"text": ".mem_axi4(u_data_sram_axi4_if)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "fabric",
|
|
"port": "sram_gateway_axi4",
|
|
"expression": "u_data_sram_axi4_if"
|
|
},
|
|
{
|
|
"node": "ram",
|
|
"port": "mem_axi4",
|
|
"expression": "u_data_sram_axi4_if"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "apb.p1",
|
|
"to": "ram.p1",
|
|
"kind": "data",
|
|
"label": "APB4 / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"text": ".cfg_apb4(u_sram_cfg_if)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "ram",
|
|
"port": "cfg_apb4",
|
|
"expression": "u_sram_cfg_if"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "ram.p2",
|
|
"to": "banks.p2",
|
|
"kind": "data",
|
|
"label": "WRITE / 64",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/memory/onchip_ram.sv",
|
|
"text": ".data_i(s_mem_wdata[31:0])"
|
|
},
|
|
{
|
|
"file": "rtl/ip/memory/onchip_ram.sv",
|
|
"text": ".data_i(s_mem_wdata[63:32])"
|
|
}
|
|
],
|
|
"instance_ports": []
|
|
}
|
|
],
|
|
"note": "PRODUCT uses a native AXI64/ID7 SRAM target in the HP clock domain. The selected IHP130 profile supplies 32 KiB. Bank count and physical macro organization are distinct from the address aperture."
|
|
},
|
|
"xpi": {
|
|
"nodes": [
|
|
{
|
|
"id": "reg",
|
|
"title": "APB4 registers\nLUT / slot configuration",
|
|
"x": 0.0,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/storage/apb4_xpi.sv",
|
|
"rtl/ip/storage/xpi_reg.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/storage/apb4_xpi.sv",
|
|
"name": "u_xpi_reg",
|
|
"module": "xpi_reg",
|
|
"declaration_file": "rtl/ip/storage/xpi_reg.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "indirect",
|
|
"title": "Indirect / status polling\nPIO and stream byte path",
|
|
"x": 6.3,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "out",
|
|
"width": 8,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/storage/apb4_xpi.sv",
|
|
"rtl/ip/storage/xpi_indirect.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/storage/apb4_xpi.sv",
|
|
"name": "u_xpi_indirect",
|
|
"module": "xpi_indirect",
|
|
"declaration_file": "rtl/ip/storage/xpi_indirect.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "mm",
|
|
"title": "Memory-map adapter\nAXI32 transactions",
|
|
"x": 0.0,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p1",
|
|
"direction": "out",
|
|
"width": 8,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/storage/apb4_xpi.sv",
|
|
"rtl/ip/storage/xpi_mm.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/storage/apb4_xpi.sv",
|
|
"name": "u_xpi_mm",
|
|
"module": "xpi_mm",
|
|
"declaration_file": "rtl/ip/storage/xpi_mm.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "owner",
|
|
"title": "Request / byte arbitration\nwrapper ownership state",
|
|
"x": 6.3,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p1",
|
|
"direction": "in",
|
|
"width": 8,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "in",
|
|
"width": 8,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p3",
|
|
"direction": "out",
|
|
"width": 8,
|
|
"side": "east"
|
|
},
|
|
{
|
|
"id": "p4",
|
|
"direction": "in",
|
|
"width": 8,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/storage/apb4_xpi.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "core",
|
|
"title": "LUT command sequencer\nserial transfer core",
|
|
"x": 12.6,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p3",
|
|
"direction": "in",
|
|
"width": 8,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p4",
|
|
"direction": "out",
|
|
"width": 8,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p5",
|
|
"direction": "out",
|
|
"width": null,
|
|
"side": "south",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/storage/apb4_xpi.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/storage/apb4_xpi.sv",
|
|
"name": "u_xpi_core",
|
|
"module": "`APB4_XPI_CORE_MODULE"
|
|
}
|
|
},
|
|
{
|
|
"id": "pads",
|
|
"title": "XPI interface\nCS / SCK / IO",
|
|
"x": 12.6,
|
|
"y": 0.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p5",
|
|
"direction": "in",
|
|
"width": null,
|
|
"side": "north",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/storage/apb4_xpi.sv"
|
|
]
|
|
}
|
|
],
|
|
"edges": [
|
|
{
|
|
"from": "reg.p0",
|
|
"to": "indirect.p0",
|
|
"kind": "control",
|
|
"label": "START",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/storage/apb4_xpi.sv",
|
|
"text": ".indirect_start_o(s_indirect_start)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/storage/apb4_xpi.sv",
|
|
"text": ".indirect_start_i(s_indirect_start)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/storage/apb4_xpi.sv",
|
|
"scope": "apb4_xpi",
|
|
"symbol": "s_indirect_start",
|
|
"bits": 1
|
|
},
|
|
{
|
|
"file": "rtl/ip/storage/apb4_xpi.sv",
|
|
"scope": "apb4_xpi",
|
|
"symbol": "s_indirect_start",
|
|
"bits": 1
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "indirect_start_o",
|
|
"expression": "s_indirect_start"
|
|
},
|
|
{
|
|
"node": "indirect",
|
|
"port": "indirect_start_i",
|
|
"expression": "s_indirect_start"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "mm.p1",
|
|
"to": "owner.p1",
|
|
"kind": "data",
|
|
"label": "TX / 8",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/storage/apb4_xpi.sv",
|
|
"text": ".core_tx_data_o(s_mm_tx_data)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/storage/apb4_xpi.sv",
|
|
"scope": "apb4_xpi",
|
|
"symbol": "s_mm_tx_data",
|
|
"bits": 8
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "mm",
|
|
"port": "core_tx_data_o",
|
|
"expression": "s_mm_tx_data"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "indirect.p2",
|
|
"to": "owner.p2",
|
|
"kind": "data",
|
|
"label": "TX / 8",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/storage/apb4_xpi.sv",
|
|
"text": ".core_tx_data_o(s_indirect_tx_data)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/storage/apb4_xpi.sv",
|
|
"scope": "apb4_xpi",
|
|
"symbol": "s_indirect_tx_data",
|
|
"bits": 8
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "indirect",
|
|
"port": "core_tx_data_o",
|
|
"expression": "s_indirect_tx_data"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "owner.p3",
|
|
"to": "core.p3",
|
|
"kind": "data",
|
|
"label": "TX / 8",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/storage/apb4_xpi.sv",
|
|
"text": "assign s_core_tx_data = (s_owner_q == OwnerMm) ? s_mm_tx_data : s_indirect_tx_data;"
|
|
},
|
|
{
|
|
"file": "rtl/ip/storage/apb4_xpi.sv",
|
|
"text": ".tx_data_i(s_core_tx_data)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/storage/apb4_xpi.sv",
|
|
"scope": "apb4_xpi",
|
|
"symbol": "s_core_tx_data",
|
|
"bits": 8
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "tx_data_i",
|
|
"expression": "s_core_tx_data"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "core.p4",
|
|
"to": "owner.p4",
|
|
"kind": "data",
|
|
"label": "RX / 8",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/storage/apb4_xpi.sv",
|
|
"text": ".rx_data_o(s_core_rx_data)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/storage/apb4_xpi.sv",
|
|
"scope": "apb4_xpi",
|
|
"symbol": "s_core_rx_data",
|
|
"bits": 8
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "rx_data_o",
|
|
"expression": "s_core_rx_data"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "core.p5",
|
|
"to": "pads.p5",
|
|
"kind": "data",
|
|
"label": "XPI signals",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/storage/apb4_xpi.sv",
|
|
"text": ".xpi(xpi)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "xpi",
|
|
"expression": "xpi"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
}
|
|
],
|
|
"note": "Memory-mapped and indirect requests share ownership of the LUT/serial core. Request arbitration and byte selection are logic in the wrapper. The PRODUCT AXI64 data-plane route to XPI is read-only; indirect program/erase uses its command path."
|
|
},
|
|
"dvp": {
|
|
"nodes": [
|
|
{
|
|
"id": "reg",
|
|
"title": "APB4 registers\ncapture / stream control",
|
|
"x": 0.0,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "out",
|
|
"width": 128,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/multimedia/axi4s_dvp.sv",
|
|
"rtl/ip/multimedia/dvp_reg.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/multimedia/axi4s_dvp.sv",
|
|
"name": "u_dvp_reg",
|
|
"module": "dvp_reg",
|
|
"declaration_file": "rtl/ip/multimedia/dvp_reg.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "cfg",
|
|
"title": "Configuration CDC\nsystem to pixel",
|
|
"x": 6.3,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "in",
|
|
"width": 128,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "out",
|
|
"width": 128,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/multimedia/axi4s_dvp.sv",
|
|
"rtl/managed/clusterip/common/rtl/cdc/cdc_2phase.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/multimedia/axi4s_dvp.sv",
|
|
"name": "u_dvp_config_cdc",
|
|
"module": "cdc_2phase",
|
|
"declaration_file": "rtl/managed/clusterip/common/rtl/cdc/cdc_2phase.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "core",
|
|
"title": "Pixel-domain core\nRGB / YUV packing",
|
|
"x": 12.6,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p1",
|
|
"direction": "in",
|
|
"width": 128,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "in",
|
|
"width": 8,
|
|
"side": "south"
|
|
},
|
|
{
|
|
"id": "p3",
|
|
"direction": "out",
|
|
"width": 42,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/multimedia/axi4s_dvp.sv",
|
|
"rtl/ip/multimedia/dvp_core.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/multimedia/axi4s_dvp.sv",
|
|
"name": "u_dvp_core",
|
|
"module": "dvp_core",
|
|
"declaration_file": "rtl/ip/multimedia/dvp_core.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "pads",
|
|
"title": "Camera inputs\nPCLK / VSYNC / HREF / D8",
|
|
"x": 12.6,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p2",
|
|
"direction": "out",
|
|
"width": 8,
|
|
"side": "north"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/multimedia/axi4s_dvp.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "fifo",
|
|
"title": "Payload CDC FIFO\npixel to system",
|
|
"x": 6.3,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p3",
|
|
"direction": "in",
|
|
"width": 42,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p4",
|
|
"direction": "out",
|
|
"width": 42,
|
|
"side": "west"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/multimedia/axi4s_dvp.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/multimedia/axi4s_dvp.sv",
|
|
"name": "u_dvp_payload_fifo",
|
|
"module": "cdc_fifo_warm_flush"
|
|
}
|
|
},
|
|
{
|
|
"id": "sink",
|
|
"title": "PIO / stream sink\ncentral DMA endpoint",
|
|
"x": 0.0,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p4",
|
|
"direction": "in",
|
|
"width": 42,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/multimedia/axi4s_dvp.sv"
|
|
]
|
|
}
|
|
],
|
|
"edges": [
|
|
{
|
|
"from": "reg.p0",
|
|
"to": "cfg.p0",
|
|
"kind": "control",
|
|
"label": "CFG / 128",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/multimedia/axi4s_dvp.sv",
|
|
"text": ".cfg_o(s_cfg_sys)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/multimedia/axi4s_dvp.sv",
|
|
"text": ".src_data_i(s_cfg_sys)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/multimedia/axi4s_dvp.sv",
|
|
"scope": "axi4s_dvp",
|
|
"symbol": "s_cfg_sys",
|
|
"bits": 128
|
|
},
|
|
{
|
|
"file": "rtl/ip/multimedia/axi4s_dvp.sv",
|
|
"scope": "axi4s_dvp",
|
|
"symbol": "s_cfg_sys",
|
|
"bits": 128
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "cfg_o",
|
|
"expression": "s_cfg_sys"
|
|
},
|
|
{
|
|
"node": "cfg",
|
|
"port": "src_data_i",
|
|
"expression": "s_cfg_sys"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "cfg.p1",
|
|
"to": "core.p1",
|
|
"kind": "control",
|
|
"label": "CFG / 128",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/multimedia/axi4s_dvp.sv",
|
|
"text": ".dst_data_o(s_cfg_pclk_q)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/multimedia/axi4s_dvp.sv",
|
|
"text": ".cfg_i(s_cfg_pclk_q)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/multimedia/axi4s_dvp.sv",
|
|
"scope": "axi4s_dvp",
|
|
"symbol": "s_cfg_pclk_q",
|
|
"bits": 128
|
|
},
|
|
{
|
|
"file": "rtl/ip/multimedia/axi4s_dvp.sv",
|
|
"scope": "axi4s_dvp",
|
|
"symbol": "s_cfg_pclk_q",
|
|
"bits": 128
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "cfg",
|
|
"port": "dst_data_o",
|
|
"expression": "s_cfg_pclk_q"
|
|
},
|
|
{
|
|
"node": "core",
|
|
"port": "cfg_i",
|
|
"expression": "s_cfg_pclk_q"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "pads.p2",
|
|
"to": "core.p2",
|
|
"kind": "data",
|
|
"label": "PIXEL / 8",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/multimedia/axi4s_dvp.sv",
|
|
"text": ".dat_i(dvp.dat_i)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "dat_i",
|
|
"expression": "dvp.dat_i"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "core.p3",
|
|
"to": "fifo.p3",
|
|
"kind": "data",
|
|
"label": "PAYLOAD / 42",
|
|
"style": "zigzag",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/multimedia/axi4s_dvp.sv",
|
|
"text": ".push_data_o(s_core_push_data)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/multimedia/axi4s_dvp.sv",
|
|
"text": ".src_data_i(s_core_push_data)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/multimedia/axi4s_dvp.sv",
|
|
"scope": "axi4s_dvp",
|
|
"symbol": "s_core_push_data",
|
|
"bits": 42
|
|
},
|
|
{
|
|
"file": "rtl/ip/multimedia/axi4s_dvp.sv",
|
|
"scope": "axi4s_dvp",
|
|
"symbol": "s_core_push_data",
|
|
"bits": 42
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "push_data_o",
|
|
"expression": "s_core_push_data"
|
|
},
|
|
{
|
|
"node": "fifo",
|
|
"port": "src_data_i",
|
|
"expression": "s_core_push_data"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "fifo.p4",
|
|
"to": "sink.p4",
|
|
"kind": "data",
|
|
"label": "FIFO / 42",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/multimedia/axi4s_dvp.sv",
|
|
"text": ".dst_data_o(s_fifo_dst_data)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/multimedia/axi4s_dvp.sv",
|
|
"scope": "axi4s_dvp",
|
|
"symbol": "s_fifo_dst_data",
|
|
"bits": 42
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "fifo",
|
|
"port": "dst_data_o",
|
|
"expression": "s_fifo_dst_data"
|
|
}
|
|
]
|
|
}
|
|
],
|
|
"note": "Configuration crosses into the pixel domain; 42-bit pixel/event payloads return through a warm-flush CDC FIFO. PIO or AXI4-Stream consumes the same captured payload. No direct DVP-to-JPEG connection is implied."
|
|
},
|
|
"jpeg": {
|
|
"nodes": [
|
|
{
|
|
"id": "reg",
|
|
"title": "APB4 registers\ndirect / ring job configuration",
|
|
"x": 0.0,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/multimedia/apb4_jpeg.sv",
|
|
"rtl/ip/multimedia/jpeg_reg.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/multimedia/apb4_jpeg.sv",
|
|
"name": "u_reg",
|
|
"module": "jpeg_reg",
|
|
"declaration_file": "rtl/ip/multimedia/jpeg_reg.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "job",
|
|
"title": "Job / descriptor sequencer\nwrapper state and surfaces",
|
|
"x": 6.3,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "east"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "south"
|
|
},
|
|
{
|
|
"id": "p3",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/multimedia/apb4_jpeg.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "dma",
|
|
"title": "Private AXI64 DMA\nread / write line engines",
|
|
"x": 12.6,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p1",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p6",
|
|
"direction": "out",
|
|
"width": 64,
|
|
"side": "north"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/multimedia/apb4_jpeg.sv",
|
|
"rtl/ip/multimedia/jpeg_dma.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/multimedia/apb4_jpeg.sv",
|
|
"name": "u_dma",
|
|
"module": "jpeg_dma",
|
|
"declaration_file": "rtl/ip/multimedia/jpeg_dma.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "encode",
|
|
"title": "JPEG encode core\npixels to entropy stream",
|
|
"x": 0.0,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p2",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p4",
|
|
"direction": "out",
|
|
"width": null,
|
|
"side": "east",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/multimedia/apb4_jpeg.sv",
|
|
"rtl/ip/multimedia/jpeg_encode_core.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/multimedia/apb4_jpeg.sv",
|
|
"name": "u_encode_core",
|
|
"module": "jpeg_encode_core",
|
|
"declaration_file": "rtl/ip/multimedia/jpeg_encode_core.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "coeff",
|
|
"title": "Shared coefficient engine\ntransform / quantization",
|
|
"x": 6.3,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p4",
|
|
"direction": "in",
|
|
"width": null,
|
|
"side": "west",
|
|
"bundle": true
|
|
},
|
|
{
|
|
"id": "p5",
|
|
"direction": "in",
|
|
"width": null,
|
|
"side": "east",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/multimedia/apb4_jpeg.sv",
|
|
"rtl/ip/multimedia/jpeg_coefficient_engine.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/multimedia/apb4_jpeg.sv",
|
|
"name": "u_coefficient_engine",
|
|
"module": "jpeg_coefficient_engine",
|
|
"declaration_file": "rtl/ip/multimedia/jpeg_coefficient_engine.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "decode",
|
|
"title": "JPEG decode core\nentropy to pixel surfaces",
|
|
"x": 12.6,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p3",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p5",
|
|
"direction": "out",
|
|
"width": null,
|
|
"side": "west",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/multimedia/apb4_jpeg.sv",
|
|
"rtl/ip/multimedia/jpeg_decode_core.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/multimedia/apb4_jpeg.sv",
|
|
"name": "u_decode_core",
|
|
"module": "jpeg_decode_core",
|
|
"declaration_file": "rtl/ip/multimedia/jpeg_decode_core.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "memory",
|
|
"title": "AXI64 shared memory\nraster / stream / descriptor",
|
|
"x": 12.6,
|
|
"y": 10.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p6",
|
|
"direction": "in",
|
|
"width": 64,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/multimedia/apb4_jpeg.sv"
|
|
]
|
|
}
|
|
],
|
|
"edges": [
|
|
{
|
|
"from": "reg.p0",
|
|
"to": "job.p0",
|
|
"kind": "data",
|
|
"label": "JOB / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/multimedia/apb4_jpeg.sv",
|
|
"text": ".job_config_o(s_reg_job_config)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/multimedia/apb4_jpeg.sv",
|
|
"scope": "apb4_jpeg",
|
|
"symbol": "s_reg_job_config",
|
|
"bits": 32
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "job_config_o",
|
|
"expression": "s_reg_job_config"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "job.p1",
|
|
"to": "dma.p1",
|
|
"kind": "control",
|
|
"label": "READ start",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/multimedia/apb4_jpeg.sv",
|
|
"text": ".read_start_i(s_dma_read_start)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/multimedia/apb4_jpeg.sv",
|
|
"scope": "apb4_jpeg",
|
|
"symbol": "s_dma_read_start",
|
|
"bits": 1
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "dma",
|
|
"port": "read_start_i",
|
|
"expression": "s_dma_read_start"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "job.p2",
|
|
"to": "encode.p2",
|
|
"kind": "control",
|
|
"label": "ENCODE start",
|
|
"style": "zigzag",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/multimedia/apb4_jpeg.sv",
|
|
"text": ".start_i(s_encode_start)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/multimedia/apb4_jpeg.sv",
|
|
"scope": "apb4_jpeg",
|
|
"symbol": "s_encode_start",
|
|
"bits": 1
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "encode",
|
|
"port": "start_i",
|
|
"expression": "s_encode_start"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "job.p3",
|
|
"to": "decode.p3",
|
|
"kind": "control",
|
|
"label": "DECODE start",
|
|
"style": "zigzag",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/multimedia/apb4_jpeg.sv",
|
|
"text": ".start_i(s_decode_start)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/multimedia/apb4_jpeg.sv",
|
|
"scope": "apb4_jpeg",
|
|
"symbol": "s_decode_start",
|
|
"bits": 1
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "decode",
|
|
"port": "start_i",
|
|
"expression": "s_decode_start"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "encode.p4",
|
|
"to": "coeff.p4",
|
|
"kind": "data",
|
|
"label": "ENC block",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/multimedia/apb4_jpeg.sv",
|
|
"text": ".coefficient_block_o(s_encode_coefficient_block)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "encode",
|
|
"port": "coefficient_block_o",
|
|
"expression": "s_encode_coefficient_block"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "decode.p5",
|
|
"to": "coeff.p5",
|
|
"kind": "data",
|
|
"label": "DEC block",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/multimedia/apb4_jpeg.sv",
|
|
"text": ".coefficient_block_o(s_decode_coefficient_block)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "decode",
|
|
"port": "coefficient_block_o",
|
|
"expression": "s_decode_coefficient_block"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "dma.p6",
|
|
"to": "memory.p6",
|
|
"kind": "data",
|
|
"label": "AXI64 / 1R+1W",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/multimedia/apb4_jpeg.sv",
|
|
"text": ".axi4(axi4)"
|
|
},
|
|
{
|
|
"file": "rtl/mini/top/axi4_data_crossbar.sv",
|
|
"text": "function automatic logic [CountWidth-1:0] master_read_limit(input int unsigned master); if ((master <= 2) || (master == 7)) return CountWidth'(4); if ((master == 3) || (master == 4)) return CountWidth'(2); if ((master == 5) || (master == 6) || (master == 8) || (master == 9)) return CountWidth'(1); return '0; endfunction"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "dma",
|
|
"port": "axi4",
|
|
"expression": "axi4"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
}
|
|
],
|
|
"note": "Direct and ring jobs share one active codec job and a private memory DMA. Encode/decode surfaces and entropy streams are multiplexed by wrapper state; the shared coefficient engine is not a second independent job lane. The JPEG AXI64 interface is wired with one normal read and one normal write credit for master slot 6; complete JPEG system qualification remains separate."
|
|
},
|
|
"usb2": {
|
|
"nodes": [
|
|
{
|
|
"id": "reg",
|
|
"title": "APB4 registers\nrole / endpoints / channels",
|
|
"x": 0.0,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "out",
|
|
"width": null,
|
|
"side": "east",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/usb/apb4_usb2.sv",
|
|
"rtl/ip/usb/usb2_reg.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/usb/apb4_usb2.sv",
|
|
"name": "u_reg",
|
|
"module": "usb2_reg",
|
|
"declaration_file": "rtl/ip/usb/usb2_reg.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "scheduler",
|
|
"title": "Endpoint / channel\npacket scheduler",
|
|
"x": 6.3,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "in",
|
|
"width": null,
|
|
"side": "west",
|
|
"bundle": true
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "east"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/usb/apb4_usb2.sv",
|
|
"rtl/ip/usb/usb2_scheduler.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/usb/apb4_usb2.sv",
|
|
"name": "u_scheduler",
|
|
"module": "usb2_scheduler",
|
|
"declaration_file": "rtl/ip/usb/usb2_scheduler.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "dma",
|
|
"title": "Private AXI32 DMA\ndescriptor fetch / writeback",
|
|
"x": 12.6,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p1",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p4",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/usb/apb4_usb2.sv",
|
|
"rtl/ip/usb/usb2_dma.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/usb/apb4_usb2.sv",
|
|
"name": "u_dma",
|
|
"module": "usb2_dma",
|
|
"declaration_file": "rtl/ip/usb/usb2_dma.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "cmd",
|
|
"title": "Work command CDC\nrequest / acknowledge",
|
|
"x": 6.3,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p2",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p3",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/usb/apb4_usb2.sv",
|
|
"rtl/managed/clusterip/common/rtl/cdc/async_reqack.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/usb/apb4_usb2.sv",
|
|
"name": "u_work_cdc",
|
|
"module": "async_reqack",
|
|
"declaration_file": "rtl/managed/clusterip/common/rtl/cdc/async_reqack.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "data",
|
|
"title": "Packet stream CDC\n32 data + sidebands",
|
|
"x": 12.6,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p4",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p5",
|
|
"direction": "out",
|
|
"width": 37,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/usb/apb4_usb2.sv",
|
|
"rtl/managed/clusterip/common/rtl/cdc/cdc_fifo.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/usb/apb4_usb2.sv",
|
|
"name": "u_fill_stream_cdc",
|
|
"module": "cdc_fifo",
|
|
"declaration_file": "rtl/managed/clusterip/common/rtl/cdc/cdc_fifo.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "link",
|
|
"title": "ULPI link domain\npacket RAM / transaction core",
|
|
"x": 6.3,
|
|
"y": 0.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p3",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p5",
|
|
"direction": "in",
|
|
"width": 37,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p6",
|
|
"direction": "out",
|
|
"width": null,
|
|
"side": "west",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/usb/apb4_usb2.sv",
|
|
"rtl/ip/usb/usb2_link_domain.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/usb/apb4_usb2.sv",
|
|
"name": "u_link_domain",
|
|
"module": "usb2_link_domain",
|
|
"declaration_file": "rtl/ip/usb/usb2_link_domain.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "phy",
|
|
"title": "External ULPI PHY\n8-bit interface",
|
|
"x": 0.0,
|
|
"y": 0.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p6",
|
|
"direction": "in",
|
|
"width": null,
|
|
"side": "east",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/usb/apb4_usb2.sv"
|
|
]
|
|
}
|
|
],
|
|
"edges": [
|
|
{
|
|
"from": "reg.p0",
|
|
"to": "scheduler.p0",
|
|
"kind": "control",
|
|
"label": "EP config",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/usb/apb4_usb2.sv",
|
|
"text": ".endpoint_cfg_o(s_endpoint_cfg)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/usb/apb4_usb2.sv",
|
|
"text": ".endpoint_cfg_i(s_endpoint_cfg)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "endpoint_cfg_o",
|
|
"expression": "s_endpoint_cfg"
|
|
},
|
|
{
|
|
"node": "scheduler",
|
|
"port": "endpoint_cfg_i",
|
|
"expression": "s_endpoint_cfg"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "scheduler.p1",
|
|
"to": "dma.p1",
|
|
"kind": "control",
|
|
"label": "DMA start",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/usb/apb4_usb2.sv",
|
|
"text": ".dma_start_o(s_dma_start)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/usb/apb4_usb2.sv",
|
|
"text": ".start_i(s_dma_start)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/usb/apb4_usb2.sv",
|
|
"scope": "apb4_usb2",
|
|
"symbol": "s_dma_start",
|
|
"bits": 1
|
|
},
|
|
{
|
|
"file": "rtl/ip/usb/apb4_usb2.sv",
|
|
"scope": "apb4_usb2",
|
|
"symbol": "s_dma_start",
|
|
"bits": 1
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "scheduler",
|
|
"port": "dma_start_o",
|
|
"expression": "s_dma_start"
|
|
},
|
|
{
|
|
"node": "dma",
|
|
"port": "start_i",
|
|
"expression": "s_dma_start"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "scheduler.p2",
|
|
"to": "cmd.p2",
|
|
"kind": "control",
|
|
"label": "WORK valid",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/usb/apb4_usb2.sv",
|
|
"text": ".work_valid_o(s_work_valid_sys)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/usb/apb4_usb2.sv",
|
|
"text": ".src_valid_i(s_work_valid_sys)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/usb/apb4_usb2.sv",
|
|
"scope": "apb4_usb2",
|
|
"symbol": "s_work_valid_sys",
|
|
"bits": 1
|
|
},
|
|
{
|
|
"file": "rtl/ip/usb/apb4_usb2.sv",
|
|
"scope": "apb4_usb2",
|
|
"symbol": "s_work_valid_sys",
|
|
"bits": 1
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "scheduler",
|
|
"port": "work_valid_o",
|
|
"expression": "s_work_valid_sys"
|
|
},
|
|
{
|
|
"node": "cmd",
|
|
"port": "src_valid_i",
|
|
"expression": "s_work_valid_sys"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "cmd.p3",
|
|
"to": "link.p3",
|
|
"kind": "control",
|
|
"label": "WORK valid",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/usb/apb4_usb2.sv",
|
|
"text": ".dst_valid_o(s_work_valid_ulpi)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/usb/apb4_usb2.sv",
|
|
"text": ".work_valid_i(s_work_valid_ulpi)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/usb/apb4_usb2.sv",
|
|
"scope": "apb4_usb2",
|
|
"symbol": "s_work_valid_ulpi",
|
|
"bits": 1
|
|
},
|
|
{
|
|
"file": "rtl/ip/usb/apb4_usb2.sv",
|
|
"scope": "apb4_usb2",
|
|
"symbol": "s_work_valid_ulpi",
|
|
"bits": 1
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "cmd",
|
|
"port": "dst_valid_o",
|
|
"expression": "s_work_valid_ulpi"
|
|
},
|
|
{
|
|
"node": "link",
|
|
"port": "work_valid_i",
|
|
"expression": "s_work_valid_ulpi"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "dma.p4",
|
|
"to": "data.p4",
|
|
"kind": "data",
|
|
"label": "DATA / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/usb/apb4_usb2.sv",
|
|
"text": ".packet_out_data_o(s_fill_stream_data_sys[31:0])"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "dma",
|
|
"port": "packet_out_data_o",
|
|
"expression": "s_fill_stream_data_sys[31:0]"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "data.p5",
|
|
"to": "link.p5",
|
|
"kind": "data",
|
|
"label": "PACKET / 37",
|
|
"style": "zigzag",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/usb/apb4_usb2.sv",
|
|
"text": ".dst_data_o(s_fill_stream_data_ulpi)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/usb/apb4_usb2.sv",
|
|
"text": ".fill_stream_data_i(s_fill_stream_data_ulpi)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/usb/apb4_usb2.sv",
|
|
"scope": "apb4_usb2",
|
|
"symbol": "s_fill_stream_data_ulpi",
|
|
"bits": 37
|
|
},
|
|
{
|
|
"file": "rtl/ip/usb/apb4_usb2.sv",
|
|
"scope": "apb4_usb2",
|
|
"symbol": "s_fill_stream_data_ulpi",
|
|
"bits": 37
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "data",
|
|
"port": "dst_data_o",
|
|
"expression": "s_fill_stream_data_ulpi"
|
|
},
|
|
{
|
|
"node": "link",
|
|
"port": "fill_stream_data_i",
|
|
"expression": "s_fill_stream_data_ulpi"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "link.p6",
|
|
"to": "phy.p6",
|
|
"kind": "data",
|
|
"label": "ULPI bundle",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/usb/apb4_usb2.sv",
|
|
"text": ".ulpi(ulpi)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "link",
|
|
"port": "ulpi",
|
|
"expression": "ulpi"
|
|
}
|
|
]
|
|
}
|
|
],
|
|
"note": "System-domain scheduling and private DMA exchange commands, results and packet words with the ULPI link domain through explicit CDC channels. Packet RAM and PHY-facing state live in the link domain; this is not an EHCI register architecture."
|
|
},
|
|
"ext-l": {
|
|
"nodes": [
|
|
{
|
|
"id": "apb",
|
|
"title": "APB4 slot window\nidentity / lifecycle / ACL",
|
|
"x": 0.0,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/extension_subsystem.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "slot",
|
|
"title": "Extension slot controller\nowner / admission state",
|
|
"x": 6.3,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/extension_subsystem.sv",
|
|
"rtl/mini/top/extension_slot.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/mini/top/extension_subsystem.sv",
|
|
"name": "u_ext_l_slot",
|
|
"module": "extension_slot",
|
|
"declaration_file": "rtl/mini/top/extension_slot.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "irq",
|
|
"title": "Slot interrupt / idle\ncontrol boundary",
|
|
"x": 12.6,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p1",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "west"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/extension_subsystem.sv"
|
|
]
|
|
}
|
|
],
|
|
"edges": [
|
|
{
|
|
"from": "apb.p0",
|
|
"to": "slot.p0",
|
|
"kind": "data",
|
|
"label": "APB4 / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/extension_subsystem.sv",
|
|
"text": ".cfg_apb4(ext_l_apb4)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "slot",
|
|
"port": "cfg_apb4",
|
|
"expression": "ext_l_apb4"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "slot.p1",
|
|
"to": "irq.p1",
|
|
"kind": "control",
|
|
"label": "IRQ",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/extension_subsystem.sv",
|
|
"text": ".irq_o(ext_l_irq_o)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/mini/top/extension_subsystem.sv",
|
|
"scope": "extension_subsystem",
|
|
"symbol": "ext_l_irq_o",
|
|
"bits": 1
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "slot",
|
|
"port": "irq_o",
|
|
"expression": "ext_l_irq_o"
|
|
}
|
|
]
|
|
}
|
|
],
|
|
"note": "EXT-L is a control-only slot; no data master, stream or local SRAM is advertised."
|
|
},
|
|
"ext-h": {
|
|
"nodes": [
|
|
{
|
|
"id": "apb",
|
|
"title": "APB4 slot window\nidentity / lifecycle / ACL",
|
|
"x": 0.0,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/extension_subsystem.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "slot",
|
|
"title": "Extension slot controller\nowner / admission state",
|
|
"x": 6.3,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "east"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/extension_subsystem.sv",
|
|
"rtl/mini/top/extension_slot.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/mini/top/extension_subsystem.sv",
|
|
"name": "u_ext_h_slot",
|
|
"module": "extension_slot",
|
|
"declaration_file": "rtl/mini/top/extension_slot.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "irq",
|
|
"title": "Slot interrupt / idle\ncontrol boundary",
|
|
"x": 12.6,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p1",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "west"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/extension_subsystem.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "dma",
|
|
"title": "Extension DMA engine\nbounded memory transfer",
|
|
"x": 6.3,
|
|
"y": 0.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p2",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p3",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/extension_subsystem.sv",
|
|
"rtl/mini/top/extension_dma_master.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/mini/top/extension_subsystem.sv",
|
|
"name": "u_ext_h_dma",
|
|
"module": "extension_dma_master",
|
|
"declaration_file": "rtl/mini/top/extension_dma_master.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "memory",
|
|
"title": "AXI32 master\nHP data-plane adapter",
|
|
"x": 12.6,
|
|
"y": 0.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p3",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "west"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/extension_subsystem.sv"
|
|
]
|
|
}
|
|
],
|
|
"edges": [
|
|
{
|
|
"from": "apb.p0",
|
|
"to": "slot.p0",
|
|
"kind": "data",
|
|
"label": "APB4 / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/extension_subsystem.sv",
|
|
"text": ".cfg_apb4(ext_h_apb4)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "slot",
|
|
"port": "cfg_apb4",
|
|
"expression": "ext_h_apb4"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "slot.p1",
|
|
"to": "irq.p1",
|
|
"kind": "control",
|
|
"label": "IRQ",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/extension_subsystem.sv",
|
|
"text": ".irq_o(ext_h_irq_o)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/mini/top/extension_subsystem.sv",
|
|
"scope": "extension_subsystem",
|
|
"symbol": "ext_h_irq_o",
|
|
"bits": 1
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "slot",
|
|
"port": "irq_o",
|
|
"expression": "ext_h_irq_o"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "slot.p2",
|
|
"to": "dma.p2",
|
|
"kind": "control",
|
|
"label": "START",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/extension_subsystem.sv",
|
|
"text": ".dma_start_o(s_ext_h_dma_start)"
|
|
},
|
|
{
|
|
"file": "rtl/mini/top/extension_subsystem.sv",
|
|
"text": ".start_i(s_ext_h_dma_start)"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/mini/top/extension_subsystem.sv",
|
|
"scope": "extension_subsystem",
|
|
"symbol": "s_ext_h_dma_start",
|
|
"bits": 1
|
|
},
|
|
{
|
|
"file": "rtl/mini/top/extension_subsystem.sv",
|
|
"scope": "extension_subsystem",
|
|
"symbol": "s_ext_h_dma_start",
|
|
"bits": 1
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "slot",
|
|
"port": "dma_start_o",
|
|
"expression": "s_ext_h_dma_start"
|
|
},
|
|
{
|
|
"node": "dma",
|
|
"port": "start_i",
|
|
"expression": "s_ext_h_dma_start"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "dma.p3",
|
|
"to": "memory.p3",
|
|
"kind": "data",
|
|
"label": "AXI4 / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/extension_subsystem.sv",
|
|
"text": ".axi4(ext_h_axi4)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "dma",
|
|
"port": "axi4",
|
|
"expression": "ext_h_axi4"
|
|
}
|
|
]
|
|
}
|
|
],
|
|
"note": "EXT-H data-master admission is capability- and lifecycle-gated. Its DMA path is bounded by read/write ACLs, timeout and quiesce/reset state. Stream and local-SRAM support follow the committed slot definition."
|
|
},
|
|
"mpw-timer": {
|
|
"nodes": [
|
|
{
|
|
"id": "apb",
|
|
"title": "Selected MPW APB4\nuser-IP window",
|
|
"x": 0.0,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "out",
|
|
"width": null,
|
|
"side": "east",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/managed/mpw/ip/username1/user_ip_design.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "core",
|
|
"title": "User timer\n8-bit divider / 16-bit count",
|
|
"x": 6.3,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "in",
|
|
"width": null,
|
|
"side": "west",
|
|
"bundle": true
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "out",
|
|
"width": null,
|
|
"side": "east",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/managed/mpw/ip/username1/user_ip_design.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "gpio",
|
|
"title": "User GPIO interface\nselected pad handoff",
|
|
"x": 12.6,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p1",
|
|
"direction": "in",
|
|
"width": null,
|
|
"side": "west",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/managed/mpw/ip/username1/user_ip_design.sv"
|
|
]
|
|
}
|
|
],
|
|
"edges": [
|
|
{
|
|
"from": "apb.p0",
|
|
"to": "core.p0",
|
|
"kind": "data",
|
|
"label": "APB writes",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/managed/mpw/ip/username1/user_ip_design.sv",
|
|
"text": "assign s_apb_wr_hdshk = apb.psel && apb.penable && apb.pwrite;"
|
|
}
|
|
],
|
|
"instance_ports": []
|
|
},
|
|
{
|
|
"from": "core.p1",
|
|
"to": "gpio.p1",
|
|
"kind": "data",
|
|
"label": "GPIO out",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/managed/mpw/ip/username1/user_ip_design.sv",
|
|
"text": "assign gpio.do_o = {`USER_GPIO_NUM{s_gpio_rev_q}};"
|
|
}
|
|
],
|
|
"instance_ports": []
|
|
}
|
|
],
|
|
"note": "Legacy MPW selection only. This user-IP interface is not an additional PRODUCT peripheral; its ID and GPIO handoff remain controlled by the compatibility profile."
|
|
},
|
|
"mpw-gpio": {
|
|
"nodes": [
|
|
{
|
|
"id": "apb",
|
|
"title": "Selected MPW APB4\nuser-IP window",
|
|
"x": 0.0,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "out",
|
|
"width": null,
|
|
"side": "east",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/managed/mpw/ip/username2/user_ip_design.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "core",
|
|
"title": "User GPIO register state\noutput / enable / input",
|
|
"x": 6.3,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "in",
|
|
"width": null,
|
|
"side": "west",
|
|
"bundle": true
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "out",
|
|
"width": null,
|
|
"side": "east",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/managed/mpw/ip/username2/user_ip_design.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "gpio",
|
|
"title": "User GPIO interface\nselected pad handoff",
|
|
"x": 12.6,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p1",
|
|
"direction": "in",
|
|
"width": null,
|
|
"side": "west",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/managed/mpw/ip/username2/user_ip_design.sv"
|
|
]
|
|
}
|
|
],
|
|
"edges": [
|
|
{
|
|
"from": "apb.p0",
|
|
"to": "core.p0",
|
|
"kind": "data",
|
|
"label": "APB writes",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/managed/mpw/ip/username2/user_ip_design.sv",
|
|
"text": "assign s_apb_wr_hdshk = apb.psel && apb.penable && apb.pwrite;"
|
|
}
|
|
],
|
|
"instance_ports": []
|
|
},
|
|
{
|
|
"from": "core.p1",
|
|
"to": "gpio.p1",
|
|
"kind": "data",
|
|
"label": "GPIO out",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/managed/mpw/ip/username2/user_ip_design.sv",
|
|
"text": "assign gpio.do_o = s_gpio_do_q;"
|
|
}
|
|
],
|
|
"instance_ports": []
|
|
}
|
|
],
|
|
"note": "Legacy MPW selection only. This user-IP interface is not an additional PRODUCT peripheral; its ID and GPIO handoff remain controlled by the compatibility profile."
|
|
},
|
|
"system-fabric": {
|
|
"nodes": [
|
|
{
|
|
"id": "lp",
|
|
"title": "Hazard3 LP management\nAXI32 source",
|
|
"x": 0.0,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/core_wrapper.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "hp",
|
|
"title": "VexiiRiscv HP\nI-cache / D-cache",
|
|
"x": 6.3,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p1",
|
|
"direction": "out",
|
|
"width": 64,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/retrosoc.sv",
|
|
"rtl/mini/top/hp_subsystem.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_hp_subsystem",
|
|
"module": "hp_subsystem",
|
|
"declaration_file": "rtl/mini/top/hp_subsystem.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "devices",
|
|
"title": "DMA / I/O / JPEG / EXT-H\nmaster groups and adapters",
|
|
"x": 12.6,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p2",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/retrosoc.sv",
|
|
"rtl/mini/top/apb4_periph.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_apb4_periph",
|
|
"module": "apb4_periph",
|
|
"declaration_file": "rtl/mini/top/apb4_periph.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "router",
|
|
"title": "LP management router\ncontrol / memory split",
|
|
"x": 0.0,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p3",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "east"
|
|
},
|
|
{
|
|
"id": "p4",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/retrosoc.sv",
|
|
"rtl/mini/top/axi4_mgmt_router.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_mgmt_router",
|
|
"module": "axi4_mgmt_router",
|
|
"declaration_file": "rtl/mini/top/axi4_mgmt_router.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "fabric",
|
|
"title": "HP-domain AXI64 plane\narbitration / ACL / fault",
|
|
"x": 6.3,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p1",
|
|
"direction": "in",
|
|
"width": 64,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p3",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p5",
|
|
"direction": "out",
|
|
"width": 64,
|
|
"side": "east"
|
|
},
|
|
{
|
|
"id": "p6",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "south"
|
|
},
|
|
{
|
|
"id": "ga",
|
|
"direction": "in",
|
|
"width": 64,
|
|
"side": "east"
|
|
},
|
|
{
|
|
"id": "np",
|
|
"direction": "in",
|
|
"width": 64,
|
|
"side": "west"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/retrosoc.sv",
|
|
"rtl/mini/top/soc_data_plane.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_data_plane",
|
|
"module": "soc_data_plane",
|
|
"declaration_file": "rtl/mini/top/soc_data_plane.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "sram",
|
|
"title": "HP-domain SRAM\nnative AXI64 / ID7",
|
|
"x": 12.6,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p5",
|
|
"direction": "in",
|
|
"width": 64,
|
|
"side": "west"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/retrosoc.sv",
|
|
"rtl/ip/memory/onchip_ram.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_onchip_ram",
|
|
"module": "onchip_ram",
|
|
"declaration_file": "rtl/ip/memory/onchip_ram.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "control",
|
|
"title": "Control bus / PCLK CDC\nAPB peripheral/system islands",
|
|
"x": 0.0,
|
|
"y": 0.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p4",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "north"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/retrosoc.sv",
|
|
"rtl/mini/top/axi4_bus.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"name": "u_bus",
|
|
"module": "axi4_bus",
|
|
"declaration_file": "rtl/mini/top/axi4_bus.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "external",
|
|
"title": "Memory CDC / adapters\nSDRAM / QPI / OPI / XPI",
|
|
"x": 6.3,
|
|
"y": 0.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p6",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "north"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/retrosoc.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "ga2d",
|
|
"title": "GA2D private AXI64\ngate / CDC / master 8",
|
|
"x": 12.6,
|
|
"y": 0.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "ga",
|
|
"direction": "out",
|
|
"width": 64,
|
|
"side": "west"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/soc_data_plane.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "npu",
|
|
"title": "NPU native HP AXI64\nmaster 9 / no payload CDC",
|
|
"x": 0,
|
|
"y": -3.5,
|
|
"w": 4,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "np",
|
|
"direction": "out",
|
|
"width": 64,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/soc_data_plane.sv",
|
|
"rtl/ip/multimedia/apb4_npu.sv"
|
|
]
|
|
}
|
|
],
|
|
"edges": [
|
|
{
|
|
"from": "lp.p0",
|
|
"to": "router.p0",
|
|
"kind": "data",
|
|
"label": "AXI4 / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"text": ".source(u_mgmt_axi4_if)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "router",
|
|
"port": "source",
|
|
"expression": "u_mgmt_axi4_if"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "hp.p1",
|
|
"to": "fabric.p1",
|
|
"kind": "data",
|
|
"label": "I-cache / 64",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"text": ".icache_axi4(u_hp_icache_axi4_if)"
|
|
},
|
|
{
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"text": ".hp_icache_axi4(u_hp_icache_axi4_if)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "hp",
|
|
"port": "icache_axi4",
|
|
"expression": "u_hp_icache_axi4_if"
|
|
},
|
|
{
|
|
"node": "fabric",
|
|
"port": "hp_icache_axi4",
|
|
"expression": "u_hp_icache_axi4_if"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "devices.p2",
|
|
"to": "fabric.p2",
|
|
"kind": "data",
|
|
"label": "DMA / 32",
|
|
"style": "zigzag",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"text": ".dma_axi4(u_dma_axi4_if)"
|
|
},
|
|
{
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"text": ".dma_axi4(u_dma_axi4_if)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "devices",
|
|
"port": "dma_axi4",
|
|
"expression": "u_dma_axi4_if"
|
|
},
|
|
{
|
|
"node": "fabric",
|
|
"port": "dma_axi4",
|
|
"expression": "u_dma_axi4_if"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "router.p3",
|
|
"to": "fabric.p3",
|
|
"kind": "data",
|
|
"label": "LP mem / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"text": ".data(u_mgmt_data_axi4_if)"
|
|
},
|
|
{
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"text": ".lp_data_axi4(u_mgmt_data_axi4_if)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "router",
|
|
"port": "data",
|
|
"expression": "u_mgmt_data_axi4_if"
|
|
},
|
|
{
|
|
"node": "fabric",
|
|
"port": "lp_data_axi4",
|
|
"expression": "u_mgmt_data_axi4_if"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "router.p4",
|
|
"to": "control.p4",
|
|
"kind": "data",
|
|
"label": "Control / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"text": ".control(u_mgmt_control_axi4_if)"
|
|
},
|
|
{
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"text": ".mgmt_axi4(u_mgmt_control_axi4_if)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "router",
|
|
"port": "control",
|
|
"expression": "u_mgmt_control_axi4_if"
|
|
},
|
|
{
|
|
"node": "control",
|
|
"port": "mgmt_axi4",
|
|
"expression": "u_mgmt_control_axi4_if"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "fabric.p5",
|
|
"to": "sram.p5",
|
|
"kind": "data",
|
|
"label": "AXI4 / 64",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"text": ".sram_gateway_axi4(u_data_sram_axi4_if)"
|
|
},
|
|
{
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"text": ".mem_axi4(u_data_sram_axi4_if)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "fabric",
|
|
"port": "sram_gateway_axi4",
|
|
"expression": "u_data_sram_axi4_if"
|
|
},
|
|
{
|
|
"node": "sram",
|
|
"port": "mem_axi4",
|
|
"expression": "u_data_sram_axi4_if"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "fabric.p6",
|
|
"to": "external.p6",
|
|
"kind": "data",
|
|
"label": "MEM AXI4 / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"text": ".sdram_gateway_axi4(u_data_sdram_axi4_if)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "fabric",
|
|
"port": "sdram_gateway_axi4",
|
|
"expression": "u_data_sdram_axi4_if"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "ga2d.ga",
|
|
"to": "fabric.ga",
|
|
"kind": "data",
|
|
"label": "AXI64",
|
|
"style": "zigzag",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/soc_data_plane.sv",
|
|
"text": ".DataWidth(64), .IdWidth(3)"
|
|
},
|
|
{
|
|
"file": "rtl/mini/top/soc_data_plane.sv",
|
|
"text": ".MasterIndex(4'd8)"
|
|
},
|
|
{
|
|
"file": "rtl/mini/top/soc_data_plane.sv",
|
|
"text": ".source(u_ga2d_prefixed_axi4), .sink(u_master_axi4[8])"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "npu.np",
|
|
"to": "fabric.np",
|
|
"kind": "data",
|
|
"label": "AXI64",
|
|
"style": "zigzag",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/soc_data_plane.sv",
|
|
"text": ".MasterIndex(4'd9)"
|
|
},
|
|
{
|
|
"file": "rtl/mini/top/soc_data_plane.sv",
|
|
"text": ".source(u_npu_prefixed_axi4)"
|
|
},
|
|
{
|
|
"file": "rtl/mini/top/soc_data_plane.sv",
|
|
"text": ".sink(u_master_axi4[9])"
|
|
}
|
|
]
|
|
}
|
|
],
|
|
"note": "Ten PRODUCT initiator identities feed five memory targets through width/clock adapters. GA2D is master 8 and uses 7-bit global IDs after source-prefix insertion. JPEG and GA2D each have one normal read and one normal write credit. Only the HP I-cache may issue instructions; XPI is read-only on this data plane. Interface arrows group request/response channels. NPU is a native-HP master with source ID zero, one read/one write and its own eight-beat limit; it does not pass through an I/O gateway or payload CDC."
|
|
},
|
|
"system-media": {
|
|
"nodes": [
|
|
{
|
|
"id": "camera",
|
|
"title": "External camera\npixel clock / data",
|
|
"x": 0.0,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "out",
|
|
"width": null,
|
|
"side": "east",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/apb4_periph.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "dvp",
|
|
"title": "DVP capture\npacking / pixel CDC",
|
|
"x": 6.3,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "in",
|
|
"width": null,
|
|
"side": "west",
|
|
"bundle": true
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/apb4_periph.sv",
|
|
"rtl/ip/multimedia/axi4s_dvp.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/mini/top/apb4_periph.sv",
|
|
"name": "u_axi4_dvp",
|
|
"module": "axi4s_dvp",
|
|
"declaration_file": "rtl/ip/multimedia/axi4s_dvp.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "dma",
|
|
"title": "Central DMA\nstream / memory transfers",
|
|
"x": 12.6,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p1",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "south"
|
|
},
|
|
{
|
|
"id": "p4",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/apb4_periph.sv",
|
|
"rtl/ip/peripheral/apb4_dma.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/mini/top/apb4_periph.sv",
|
|
"name": "u_apb4_dma",
|
|
"module": "apb4_dma",
|
|
"declaration_file": "rtl/ip/peripheral/apb4_dma.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "i2s",
|
|
"title": "External codec / I2S\naudio CDC and slots",
|
|
"x": 0.0,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p3",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/apb4_periph.sv",
|
|
"rtl/ip/serial/apb4_i2s.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/mini/top/apb4_periph.sv",
|
|
"name": "u_apb4_i2s",
|
|
"module": "apb4_i2s",
|
|
"declaration_file": "rtl/ip/serial/apb4_i2s.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "audio",
|
|
"title": "Audio stream router\nselected DMA / APU path",
|
|
"x": 6.3,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p3",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p4",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "north"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/apb4_periph.sv",
|
|
"rtl/ip/multimedia/apb4_apu.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/mini/top/apb4_periph.sv",
|
|
"name": "u_apb4_apu",
|
|
"module": "apb4_apu",
|
|
"declaration_file": "rtl/ip/multimedia/apb4_apu.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "memory",
|
|
"title": "Shared memory fabric\nexplicit buffer ownership",
|
|
"x": 12.6,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p2",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p5",
|
|
"direction": "in",
|
|
"width": 64,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/apb4_periph.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "jpeg",
|
|
"title": "JPEG memory job\nprivate AXI64 DMA",
|
|
"x": 6.3,
|
|
"y": 0.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p5",
|
|
"direction": "out",
|
|
"width": 64,
|
|
"side": "north"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/apb4_periph.sv",
|
|
"rtl/ip/multimedia/apb4_jpeg.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/mini/top/apb4_periph.sv",
|
|
"name": "u_apb4_jpeg",
|
|
"module": "apb4_jpeg",
|
|
"declaration_file": "rtl/ip/multimedia/apb4_jpeg.sv"
|
|
}
|
|
}
|
|
],
|
|
"edges": [
|
|
{
|
|
"from": "camera.p0",
|
|
"to": "dvp.p0",
|
|
"kind": "data",
|
|
"label": "DVP signals",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/apb4_periph.sv",
|
|
"text": ".dvp(dvp)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "dvp",
|
|
"port": "dvp",
|
|
"expression": "dvp"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "dvp.p1",
|
|
"to": "dma.p1",
|
|
"kind": "data",
|
|
"label": "Capture / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/apb4_periph.sv",
|
|
"text": ".rx_axis(u_dvp_rx_axis_if)"
|
|
},
|
|
{
|
|
"file": "rtl/mini/top/apb4_periph.sv",
|
|
"text": ".dvp_rx_axis(u_dvp_rx_axis_if)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "dvp",
|
|
"port": "rx_axis",
|
|
"expression": "u_dvp_rx_axis_if"
|
|
},
|
|
{
|
|
"node": "dma",
|
|
"port": "dvp_rx_axis",
|
|
"expression": "u_dvp_rx_axis_if"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "dma.p2",
|
|
"to": "memory.p2",
|
|
"kind": "data",
|
|
"label": "AXI4 / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/apb4_periph.sv",
|
|
"text": ".axi4(dma_axi4)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "dma",
|
|
"port": "axi4",
|
|
"expression": "dma_axi4"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "i2s.p3",
|
|
"to": "audio.p3",
|
|
"kind": "data",
|
|
"label": "Audio RX / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/apb4_periph.sv",
|
|
"text": ".rx_axis(u_i2s_rx_axis_if)"
|
|
},
|
|
{
|
|
"file": "rtl/mini/top/apb4_periph.sv",
|
|
"text": ".i2s_rx_axis(u_i2s_rx_axis_if)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "i2s",
|
|
"port": "rx_axis",
|
|
"expression": "u_i2s_rx_axis_if"
|
|
},
|
|
{
|
|
"node": "audio",
|
|
"port": "i2s_rx_axis",
|
|
"expression": "u_i2s_rx_axis_if"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "audio.p4",
|
|
"to": "dma.p4",
|
|
"kind": "data",
|
|
"label": "Selected RX / 32",
|
|
"style": "zigzag",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/apb4_periph.sv",
|
|
"text": ".dma_rx_axis(u_dma_i2s_rx_axis_if)"
|
|
},
|
|
{
|
|
"file": "rtl/mini/top/apb4_periph.sv",
|
|
"text": ".i2s_rx_axis(u_dma_i2s_rx_axis_if)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "audio",
|
|
"port": "dma_rx_axis",
|
|
"expression": "u_dma_i2s_rx_axis_if"
|
|
},
|
|
{
|
|
"node": "dma",
|
|
"port": "i2s_rx_axis",
|
|
"expression": "u_dma_i2s_rx_axis_if"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "jpeg.p5",
|
|
"to": "memory.p5",
|
|
"kind": "data",
|
|
"label": "AXI64 / 1R+1W",
|
|
"style": "zigzag",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/apb4_periph.sv",
|
|
"text": ".axi4(jpeg_axi4)"
|
|
},
|
|
{
|
|
"file": "rtl/mini/top/axi4_data_crossbar.sv",
|
|
"text": "function automatic logic [CountWidth-1:0] master_read_limit(input int unsigned master); if ((master <= 2) || (master == 7)) return CountWidth'(4); if ((master == 3) || (master == 4)) return CountWidth'(2); if ((master == 5) || (master == 6) || (master == 8) || (master == 9)) return CountWidth'(1); return '0; endfunction"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "jpeg",
|
|
"port": "axi4",
|
|
"expression": "jpeg_axi4"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
}
|
|
],
|
|
"note": "Camera capture reaches memory through central DMA; JPEG jobs use private master 6 with one read and one write normal credit. I2S TX can select DMA or supported APU WAV/FLAC output. KWS RX has an internal route but is gated off by default. Buffer ownership, complete workload qualification and external-device setup remain required."
|
|
},
|
|
"system-mpw": {
|
|
"nodes": [
|
|
{
|
|
"id": "select",
|
|
"title": "SYSCTRL legacy selection\ncore select / reset / isolation",
|
|
"x": 0.0,
|
|
"y": 7.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "out",
|
|
"width": null,
|
|
"side": "south",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/retrosoc.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "core",
|
|
"title": "Selected user core\ngenerated scalar bindings",
|
|
"x": 0.0,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "in",
|
|
"width": null,
|
|
"side": "north",
|
|
"bundle": true
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "out",
|
|
"width": null,
|
|
"side": "east",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/user_core_top.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "adapter",
|
|
"title": "RIB-to-AXI32 adapter",
|
|
"x": 6.3,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p1",
|
|
"direction": "in",
|
|
"width": null,
|
|
"side": "west",
|
|
"bundle": true
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/user_core_top.sv",
|
|
"rtl/mini/top/rib2axi4.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/mini/top/user_core_top.sv",
|
|
"name": "u_rib2axi4",
|
|
"module": "rib2axi4",
|
|
"declaration_file": "rtl/mini/top/rib2axi4.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "fabric",
|
|
"title": "MPW AXI32 integration\nreviewed generated mapping",
|
|
"x": 12.6,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p2",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "west"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/user_core_top.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "apb",
|
|
"title": "APB4 user-IP window",
|
|
"x": 0.0,
|
|
"y": 0.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p3",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/user_ip_wrapper.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "user",
|
|
"title": "Selected user-IP wrapper\nlegacy timer / GPIO",
|
|
"x": 6.3,
|
|
"y": 0.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p3",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p4",
|
|
"direction": "out",
|
|
"width": null,
|
|
"side": "east",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/user_ip_wrapper.sv",
|
|
"rtl/mini/top/user_ip_top.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/mini/top/user_ip_wrapper.sv",
|
|
"name": "u_user_ip_top",
|
|
"module": "user_ip_top",
|
|
"declaration_file": "rtl/mini/top/user_ip_top.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "pads",
|
|
"title": "User GPIO pad handoff",
|
|
"x": 12.6,
|
|
"y": 0.0,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p4",
|
|
"direction": "in",
|
|
"width": null,
|
|
"side": "west",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/mini/top/user_ip_wrapper.sv"
|
|
]
|
|
}
|
|
],
|
|
"edges": [
|
|
{
|
|
"from": "select.p0",
|
|
"to": "core.p0",
|
|
"kind": "control",
|
|
"label": "SELECT / RESET",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"text": ".sel_i(u_sysctrl_if.core_sel_o)"
|
|
},
|
|
{
|
|
"file": "rtl/mini/top/retrosoc.sv",
|
|
"text": ".core_reset_i(u_sysctrl_if.core_reset_o)"
|
|
}
|
|
],
|
|
"instance_ports": [],
|
|
"zigzag-dir": "horizontal"
|
|
},
|
|
{
|
|
"from": "core.p1",
|
|
"to": "adapter.p1",
|
|
"kind": "data",
|
|
"label": "RIB bundle",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/user_core_top.sv",
|
|
"text": ".rib(u_user_rib_if)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "adapter",
|
|
"port": "rib",
|
|
"expression": "u_user_rib_if"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "adapter.p2",
|
|
"to": "fabric.p2",
|
|
"kind": "data",
|
|
"label": "AXI4 / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/user_core_top.sv",
|
|
"text": ".axi4(axi4)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "adapter",
|
|
"port": "axi4",
|
|
"expression": "axi4"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "apb.p3",
|
|
"to": "user.p3",
|
|
"kind": "data",
|
|
"label": "APB4 / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/user_ip_wrapper.sv",
|
|
"text": ".apb(u_user_apb4_if)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "user",
|
|
"port": "apb",
|
|
"expression": "u_user_apb4_if"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "user.p4",
|
|
"to": "pads.p4",
|
|
"kind": "data",
|
|
"label": "GPIO",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/mini/top/user_ip_wrapper.sv",
|
|
"text": ".gpio(gpio)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "user",
|
|
"port": "gpio",
|
|
"expression": "gpio"
|
|
}
|
|
]
|
|
}
|
|
],
|
|
"note": "MPW compatibility only. Generated bindings select and isolate one legacy user core; they do not alter PRODUCT LP/HP architecture. User-IP selection has its own APB/GPIO wrapper and is not an extra bus master."
|
|
},
|
|
"ga2d": {
|
|
"nodes": [
|
|
{
|
|
"id": "reg",
|
|
"title": "APB4 registers\njob / status / IRQ",
|
|
"x": 0,
|
|
"y": 7,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "east"
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/multimedia/apb4_ga2d.sv",
|
|
"rtl/ip/multimedia/ga2d_reg.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/multimedia/apb4_ga2d.sv",
|
|
"name": "u_ga2d_reg",
|
|
"module": "ga2d_reg",
|
|
"declaration_file": "rtl/ip/multimedia/ga2d_reg.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "core",
|
|
"title": "Single-job core\nvalidate / run / drain",
|
|
"x": 6.3,
|
|
"y": 7,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "east"
|
|
},
|
|
{
|
|
"id": "p7",
|
|
"direction": "in",
|
|
"width": null,
|
|
"side": "south",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/multimedia/apb4_ga2d.sv",
|
|
"rtl/ip/multimedia/ga2d_core.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/multimedia/apb4_ga2d.sv",
|
|
"name": "u_ga2d_core",
|
|
"module": "ga2d_core",
|
|
"declaration_file": "rtl/ip/multimedia/ga2d_core.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "dma",
|
|
"title": "Private 2D DMA\nline / burst / FIFOs",
|
|
"x": 12.6,
|
|
"y": 7,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p2",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p3",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p4",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p5",
|
|
"direction": "out",
|
|
"width": 64,
|
|
"side": "south"
|
|
},
|
|
{
|
|
"id": "p6",
|
|
"direction": "in",
|
|
"width": 64,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/multimedia/ga2d_core.sv",
|
|
"rtl/ip/multimedia/ga2d_dma.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/multimedia/ga2d_core.sv",
|
|
"name": "u_dma",
|
|
"module": "ga2d_dma",
|
|
"declaration_file": "rtl/ip/multimedia/ga2d_dma.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "lifecycle",
|
|
"title": "Resource / HP lifecycle\nstop / clear / epoch",
|
|
"x": 0,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p7",
|
|
"direction": "out",
|
|
"width": null,
|
|
"side": "north",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/multimedia/apb4_ga2d.sv",
|
|
"rtl/mini/top/soc_data_plane.sv"
|
|
]
|
|
},
|
|
{
|
|
"id": "pixel",
|
|
"title": "Pixel conversion / blend\nopaque RGB and A8",
|
|
"x": 12.6,
|
|
"y": 10.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p3",
|
|
"direction": "in",
|
|
"width": 32,
|
|
"side": "south"
|
|
},
|
|
{
|
|
"id": "p4",
|
|
"direction": "out",
|
|
"width": 32,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/multimedia/ga2d_dma.sv",
|
|
"rtl/ip/multimedia/ga2d_pixel.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/multimedia/ga2d_dma.sv",
|
|
"name": "u_pixel",
|
|
"module": "ga2d_pixel",
|
|
"declaration_file": "rtl/ip/multimedia/ga2d_pixel.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "axi",
|
|
"title": "AXI64 transaction engine\nCDC to master 8",
|
|
"x": 12.6,
|
|
"y": 3.5,
|
|
"w": 4.0,
|
|
"h": 1.8,
|
|
"ports": [
|
|
{
|
|
"id": "p5",
|
|
"direction": "in",
|
|
"width": 64,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p6",
|
|
"direction": "out",
|
|
"width": 64,
|
|
"side": "north"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/multimedia/ga2d_dma.sv",
|
|
"rtl/ip/multimedia/ga2d_axi4_master.sv",
|
|
"rtl/mini/top/soc_data_plane.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/multimedia/ga2d_dma.sv",
|
|
"name": "u_axi4_master",
|
|
"module": "ga2d_axi4_master",
|
|
"declaration_file": "rtl/ip/multimedia/ga2d_axi4_master.sv"
|
|
}
|
|
}
|
|
],
|
|
"edges": [
|
|
{
|
|
"from": "reg.p0",
|
|
"to": "core.p0",
|
|
"kind": "control",
|
|
"label": "START",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/multimedia/apb4_ga2d.sv",
|
|
"text": ".start_i(s_start)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "start_i",
|
|
"expression": "s_start"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/multimedia/apb4_ga2d.sv",
|
|
"scope": "apb4_ga2d",
|
|
"symbol": "s_start",
|
|
"bits": 1
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "core.p1",
|
|
"to": "reg.p1",
|
|
"kind": "control",
|
|
"label": "Status",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/multimedia/apb4_ga2d.sv",
|
|
"text": ".busy_i(s_core_busy)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "busy_i",
|
|
"expression": "s_core_busy"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/multimedia/apb4_ga2d.sv",
|
|
"scope": "apb4_ga2d",
|
|
"symbol": "s_core_busy",
|
|
"bits": 1
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "core.p2",
|
|
"to": "dma.p2",
|
|
"kind": "control",
|
|
"label": "START",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/multimedia/ga2d_core.sv",
|
|
"text": ".start_i(s_dma_start)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "dma",
|
|
"port": "start_i",
|
|
"expression": "s_dma_start"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/multimedia/ga2d_core.sv",
|
|
"scope": "ga2d_core",
|
|
"symbol": "s_dma_start",
|
|
"bits": 1
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "dma.p3",
|
|
"to": "pixel.p3",
|
|
"kind": "data",
|
|
"label": "IN / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/multimedia/ga2d_dma.sv",
|
|
"text": ".foreground_pixel_i(s_foreground_pixel_q)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "pixel",
|
|
"port": "foreground_pixel_i",
|
|
"expression": "s_foreground_pixel_q"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/multimedia/ga2d_dma.sv",
|
|
"scope": "ga2d_dma",
|
|
"symbol": "s_foreground_pixel_q",
|
|
"bits": 32
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "pixel.p4",
|
|
"to": "dma.p4",
|
|
"kind": "data",
|
|
"label": "OUT / 32",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/multimedia/ga2d_dma.sv",
|
|
"text": ".pixel_o(s_processed_pixel)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "pixel",
|
|
"port": "pixel_o",
|
|
"expression": "s_processed_pixel"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/multimedia/ga2d_dma.sv",
|
|
"scope": "ga2d_dma",
|
|
"symbol": "s_processed_pixel",
|
|
"bits": 32
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "dma.p5",
|
|
"to": "axi.p5",
|
|
"kind": "data",
|
|
"label": "WR / 64",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/multimedia/ga2d_dma.sv",
|
|
"text": ".write_data_i(s_output_fifo_data)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "axi",
|
|
"port": "write_data_i",
|
|
"expression": "s_output_fifo_data"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/multimedia/ga2d_dma.sv",
|
|
"scope": "ga2d_dma",
|
|
"symbol": "s_output_fifo_data",
|
|
"bits": 64
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "axi.p6",
|
|
"to": "dma.p6",
|
|
"kind": "data",
|
|
"label": "RD / 64",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/multimedia/ga2d_dma.sv",
|
|
"text": ".read_data_o(s_read_data)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "axi",
|
|
"port": "read_data_o",
|
|
"expression": "s_read_data"
|
|
}
|
|
],
|
|
"signals": [
|
|
{
|
|
"file": "rtl/ip/multimedia/ga2d_dma.sv",
|
|
"scope": "ga2d_dma",
|
|
"symbol": "s_read_data",
|
|
"bits": 64
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "lifecycle.p7",
|
|
"to": "core.p7",
|
|
"kind": "control",
|
|
"label": "Stop / epoch",
|
|
"style": "zigzag",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/multimedia/apb4_ga2d.sv",
|
|
"text": ".resource_stop_i(resource_quiesce_i || resource_reset_i || source_stop_i)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "resource_stop_i",
|
|
"expression": "resource_quiesce_i || resource_reset_i || source_stop_i"
|
|
}
|
|
],
|
|
"zigzag-dir": "horizontal"
|
|
}
|
|
],
|
|
"note": "PCLK-domain direct single-job organization; configuration and detailed response channels are grouped. Three 32-entry data FIFOs reside in the DMA. Address gating, CDC, source-prefix insertion and target permissions form the separate master-8 integration path. There is no descriptor queue or hardware cache coherency."
|
|
},
|
|
"npu": {
|
|
"nodes": [
|
|
{
|
|
"id": "reg",
|
|
"title": "PCLK registers\njob / status / IRQ",
|
|
"x": 0,
|
|
"y": 7.6,
|
|
"w": 5.8,
|
|
"h": 2,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "east"
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "east"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/multimedia/apb4_npu.sv",
|
|
"rtl/ip/multimedia/npu_reg.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/multimedia/apb4_npu.sv",
|
|
"module": "npu_reg",
|
|
"name": "u_npu_reg",
|
|
"declaration_file": "rtl/ip/multimedia/npu_reg.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "cdc",
|
|
"title": "PCLK / HP control CDC\nmailboxes / epochs",
|
|
"x": 8.7,
|
|
"y": 7.6,
|
|
"w": 5.8,
|
|
"h": 2,
|
|
"ports": [
|
|
{
|
|
"id": "p0",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p1",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p2",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "south"
|
|
},
|
|
{
|
|
"id": "p3",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "south"
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/multimedia/apb4_npu.sv",
|
|
"rtl/ip/multimedia/npu_control_cdc.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/multimedia/apb4_npu.sv",
|
|
"module": "npu_control_cdc",
|
|
"name": "u_npu_control_cdc",
|
|
"declaration_file": "rtl/ip/multimedia/npu_control_cdc.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "core",
|
|
"title": "HP job / compute\n64-MAC / vector / requant",
|
|
"x": 8.7,
|
|
"y": 3.8,
|
|
"w": 5.8,
|
|
"h": 2,
|
|
"ports": [
|
|
{
|
|
"id": "p2",
|
|
"direction": "in",
|
|
"width": 1,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p3",
|
|
"direction": "out",
|
|
"width": 1,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p4",
|
|
"direction": "out",
|
|
"width": 64,
|
|
"side": "south"
|
|
},
|
|
{
|
|
"id": "p5",
|
|
"direction": "in",
|
|
"width": 64,
|
|
"side": "south"
|
|
},
|
|
{
|
|
"id": "p6",
|
|
"direction": "out",
|
|
"width": 64,
|
|
"side": "west"
|
|
},
|
|
{
|
|
"id": "p7",
|
|
"direction": "in",
|
|
"width": null,
|
|
"side": "west",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/multimedia/apb4_npu.sv",
|
|
"rtl/ip/multimedia/npu_core.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/multimedia/apb4_npu.sv",
|
|
"module": "npu_core",
|
|
"name": "u_npu_core",
|
|
"declaration_file": "rtl/ip/multimedia/npu_core.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "local",
|
|
"title": "Banked private SRAM\n64 KiB / 16 banks",
|
|
"x": 0,
|
|
"y": 3.8,
|
|
"w": 5.8,
|
|
"h": 2,
|
|
"ports": [
|
|
{
|
|
"id": "p6",
|
|
"direction": "in",
|
|
"width": 64,
|
|
"side": "east"
|
|
},
|
|
{
|
|
"id": "p7",
|
|
"direction": "out",
|
|
"width": null,
|
|
"side": "east",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/multimedia/apb4_npu.sv",
|
|
"rtl/ip/multimedia/npu_local_sram.sv",
|
|
"rtl/ip/multimedia/npu_scheduler.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/multimedia/npu_scheduler.sv",
|
|
"module": "npu_local_sram",
|
|
"name": "u_local_sram",
|
|
"declaration_file": "rtl/ip/multimedia/npu_local_sram.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "dma",
|
|
"title": "HP-native AXI64 DMA\nbyte edges / drain",
|
|
"x": 8.7,
|
|
"y": 0,
|
|
"w": 5.8,
|
|
"h": 2,
|
|
"ports": [
|
|
{
|
|
"id": "p4",
|
|
"direction": "in",
|
|
"width": 64,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p5",
|
|
"direction": "out",
|
|
"width": 64,
|
|
"side": "north"
|
|
},
|
|
{
|
|
"id": "p8",
|
|
"direction": "out",
|
|
"width": null,
|
|
"side": "west",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/multimedia/apb4_npu.sv",
|
|
"rtl/ip/multimedia/npu_dma.sv"
|
|
],
|
|
"instance_source": {
|
|
"file": "rtl/ip/multimedia/apb4_npu.sv",
|
|
"module": "npu_dma",
|
|
"name": "u_npu_dma",
|
|
"declaration_file": "rtl/ip/multimedia/npu_dma.sv"
|
|
}
|
|
},
|
|
{
|
|
"id": "fabric",
|
|
"title": "HP fabric / memories\nmaster 9 / policy checks",
|
|
"x": 0,
|
|
"y": 0,
|
|
"w": 5.8,
|
|
"h": 2,
|
|
"ports": [
|
|
{
|
|
"id": "p8",
|
|
"direction": "in",
|
|
"width": null,
|
|
"side": "east",
|
|
"bundle": true
|
|
}
|
|
],
|
|
"sources": [
|
|
"rtl/ip/multimedia/apb4_npu.sv",
|
|
"rtl/mini/top/soc_data_plane.sv"
|
|
]
|
|
}
|
|
],
|
|
"edges": [
|
|
{
|
|
"from": "reg.p0",
|
|
"to": "cdc.p0",
|
|
"kind": "control",
|
|
"label": "Launch",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/multimedia/apb4_npu.sv",
|
|
"text": ".launch_req_valid_i(s_launch_req_valid)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "launch_req_valid_o",
|
|
"expression": "s_launch_req_valid"
|
|
},
|
|
{
|
|
"node": "cdc",
|
|
"port": "launch_req_valid_i",
|
|
"expression": "s_launch_req_valid"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "cdc.p1",
|
|
"to": "reg.p1",
|
|
"kind": "control",
|
|
"label": "Result",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/multimedia/apb4_npu.sv",
|
|
"text": ".result_valid_i(s_result_valid)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "reg",
|
|
"port": "result_valid_i",
|
|
"expression": "s_result_valid"
|
|
},
|
|
{
|
|
"node": "cdc",
|
|
"port": "result_valid_o",
|
|
"expression": "s_result_valid"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "cdc.p2",
|
|
"to": "core.p2",
|
|
"kind": "control",
|
|
"label": "Launch",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/multimedia/apb4_npu.sv",
|
|
"text": ".launch_valid_i(s_hp_launch_valid)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "launch_valid_i",
|
|
"expression": "s_hp_launch_valid"
|
|
},
|
|
{
|
|
"node": "cdc",
|
|
"port": "hp_launch_valid_o",
|
|
"expression": "s_hp_launch_valid"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "core.p3",
|
|
"to": "cdc.p3",
|
|
"kind": "control",
|
|
"label": "Result",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/multimedia/apb4_npu.sv",
|
|
"text": ".result_valid_o(s_hp_result_valid)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "result_valid_o",
|
|
"expression": "s_hp_result_valid"
|
|
},
|
|
{
|
|
"node": "cdc",
|
|
"port": "hp_result_valid_i",
|
|
"expression": "s_hp_result_valid"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "core.p4",
|
|
"to": "dma.p4",
|
|
"kind": "data",
|
|
"label": "Write / 64",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/multimedia/apb4_npu.sv",
|
|
"text": ".write_data_i(s_dma_write_data)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "dma_write_data_o",
|
|
"expression": "s_dma_write_data"
|
|
},
|
|
{
|
|
"node": "dma",
|
|
"port": "write_data_i",
|
|
"expression": "s_dma_write_data"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "dma.p5",
|
|
"to": "core.p5",
|
|
"kind": "data",
|
|
"label": "Read / 64",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/multimedia/apb4_npu.sv",
|
|
"text": ".read_data_o(s_dma_read_data)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "core",
|
|
"port": "dma_read_data_i",
|
|
"expression": "s_dma_read_data"
|
|
},
|
|
{
|
|
"node": "dma",
|
|
"port": "read_data_o",
|
|
"expression": "s_dma_read_data"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "core.p6",
|
|
"to": "local.p6",
|
|
"kind": "data",
|
|
"label": "Pack / 64",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/multimedia/npu_scheduler.sv",
|
|
"text": ".pack_write_data_i(s_pack_write_data_hd)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "local",
|
|
"port": "pack_write_data_i",
|
|
"expression": "s_pack_write_data_hd"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "local.p7",
|
|
"to": "core.p7",
|
|
"kind": "data",
|
|
"label": "A / W banks",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/multimedia/npu_scheduler.sv",
|
|
"text": ".a_read_data_o(s_a_read_data)"
|
|
},
|
|
{
|
|
"file": "rtl/ip/multimedia/npu_scheduler.sv",
|
|
"text": ".w_read_data_o(s_w_read_data)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "local",
|
|
"port": "a_read_data_o",
|
|
"expression": "s_a_read_data"
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"from": "dma.p8",
|
|
"to": "fabric.p8",
|
|
"kind": "data",
|
|
"label": "AXI64",
|
|
"style": "direct",
|
|
"bindings": [
|
|
{
|
|
"file": "rtl/ip/multimedia/apb4_npu.sv",
|
|
"text": ".axi4(npu_axi4)"
|
|
}
|
|
],
|
|
"instance_ports": [
|
|
{
|
|
"node": "dma",
|
|
"port": "axi4",
|
|
"expression": "npu_axi4"
|
|
}
|
|
]
|
|
}
|
|
],
|
|
"note": "The HP core groups descriptor validation, scheduler, packer, MAC/vector and scalar requantizer. Two 256-byte accumulator contexts are separate from SRAM. Payload traffic stays in HP; PCLK control uses launch/result/snapshot mailboxes and epoch reconciliation. Ready, address, response and lifecycle details are grouped, not omitted from the implementation."
|
|
}
|
|
}
|