maksyuki
3ac9e73ab9
- Updated mailbox purpose tests to reflect new write order and sequence handling. - Added tests to ensure Linux-ready values match LP contract and constants match Linux helper. - Introduced tests to verify that offset changes do not hide stale Linux helpers. - Enhanced environment tests to report current locked launcher and runtime versions. - Added checks for SBT launcher presence in environment labels. - Improved full diagram tests to validate storage geometry and RSA vector configurations. - Expanded register tests to ensure crypto interrupt registers publish all events and lifecycle annotations preserve security boundaries. - Modified script tools tests to include Vexii generation validation and updated workflow assertions.
Mini SoC Integration
This directory is the Mini SoC integration boundary. Tiny owns a separate MCU integration. Shared CPU/debug, memory, bus helpers and software build logic are owned outside Mini. Filelists, build rules and tests reference their canonical shared paths directly.
- address_map contains the canonical Mini address-map input. Its generator
lives in
scripts/rtl/generate_memory_map.py. - core contains self-owned Mini core wrappers.
- dv contains behavioural testbench, device models, and Verilator harness sources.
- filelist contains canonical ordered .fl templates.
commonip.flis the full behavioral/synthesis Common source set;netlist_support.flis the explicit allowlist of testbench dependencies not already present in a synthesized netlist. - mk contains Mini simulator and formal make fragments; shared firmware rules
live in
rtl/mk/software.mk. - script contains Mini filelist generation and simulator-binding helpers.
Shared parsing/conversion helpers live in
scripts/rtl. - top contains SoC integration RTL, including
apb4_systemfor the APB4 platform block andapb4_periphfor the APB4 peripheral container.
Generated filelists, address-map products, and MPW output belong in the configured build variant, not under this directory.
The frozen NPU contract reserves a future independent
AXI64 master/resource 9, APB4 window 0x1001b000, and LP vector 33 / HP PLIC
source 12. Its PCLK control shell and HP-native compute/DMA require explicit
clock-pause, drain and epoch integration. These are phased design allocations,
not currently wired or qualified functionality; use the specification and
verification contract before implementation.
Verilator normally retains the pin-level QSPI flash model. The explicit
--fast-flash emulator option replaces only the reset slot-0 0xEB read PHY
with a byte-wide DPI backend; unsupported slots, writes, or LUTs fail rather
than silently falling back. hp-linux-sim uses this mode so TCD, DMA, AXI,
XPI memory-map, CRC, SDRAM, HP release, and Linux userspace remain in the
acceptance path without spending hours shifting the boot payload over QSPI.
hp-smoke-sim remains the pin-level protocol reference.