mirror of
https://github.com/retroSoC/retroSoC.git
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maksyuki
3addf412d6
- Added i2c_if.sv and spi_if.sv to rtl_style_audit.json for proper inclusion in style checks. - Updated test_i2c.py to reference i2c_if.sv from the serial directory instead of the cluster IP directory. - Modified test_spisd.py to point to spi_if.sv in the storage directory instead of the cluster IP directory.
39 lines
1.3 KiB
Systemverilog
39 lines
1.3 KiB
Systemverilog
// Copyright (c) 2023-2024 Miao Yuchi <miaoyuchi@ict.ac.cn>
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// i2s is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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`include "config.svh"
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module mic #(
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parameter int DATA_WIDTH = 24
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) (
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input logic sck_i,
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input logic ws_i,
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output logic sd_o
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);
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logic [DATA_WIDTH-1:0] r_right_chnl_dat = '0;
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logic [DATA_WIDTH-1:0] r_left_chnl_dat = '0;
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logic r_ws = '0;
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always @(posedge sck_i) r_ws <= #`REGISTER_DELAY ws_i;
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always @(negedge r_ws) r_left_chnl_dat <= #`REGISTER_DELAY $random;
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always @(posedge r_ws) r_right_chnl_dat <= #`REGISTER_DELAY $random;
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always @(negedge sck_i)
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if (~r_ws) begin
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sd_o <= #`REGISTER_DELAY r_left_chnl_dat[DATA_WIDTH-1];
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r_left_chnl_dat <= #`REGISTER_DELAY r_left_chnl_dat << 1;
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end else begin
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sd_o <= #`REGISTER_DELAY r_right_chnl_dat[DATA_WIDTH-1];
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r_right_chnl_dat <= #`REGISTER_DELAY r_right_chnl_dat << 1;
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end
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endmodule
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