mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
3cf9e4c6a6
- Modified dma_core to accommodate a wider data width for FIFO operations. - Updated filelists to include new DVP source files and formal verification files. - Introduced formal verification modules for DVP functionality. - Enhanced clock and reset domain configurations for DVP integration. - Added DVP interrupt handling in the IRQ topology. - Implemented a testbench for DVP to validate register access and frame processing. - Updated software build scripts to include DVP-related source files. - Adjusted the system topology to reflect the new DVP interrupt and IRQ mapping.
465 lines
19 KiB
Makefile
465 lines
19 KiB
Makefile
SHELL := /bin/bash
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.DEFAULT_GOAL := help
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.DELETE_ON_ERROR:
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ROOT_PATH ?= $(abspath $(dir $(firstword $(MAKEFILE_LIST))))
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CONFIG ?=
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LOCK_FILE ?= $(ROOT_PATH)/config/dependencies.lock.json
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ifneq ($(strip $(CONFIG)),)
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CONFIG_PATH := $(if $(filter /%,$(CONFIG)),$(CONFIG),$(ROOT_PATH)/$(CONFIG))
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ifeq ($(wildcard $(CONFIG_PATH)),)
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$(error Configuration profile not found: $(CONFIG_PATH))
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endif
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include $(CONFIG_PATH)
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PROFILE_NAME := $(basename $(notdir $(CONFIG_PATH)))
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else
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CONFIG_PATH :=
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PROFILE_NAME := manual
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endif
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ifneq ($(origin IP),undefined)
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$(error IP is no longer configurable; user IP integration is fixed)
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endif
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ifneq ($(origin CORE),undefined)
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$(error CORE has been removed; the management core is fixed to Hazard3)
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endif
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ifneq ($(origin HAVE_DEBUG),undefined)
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$(error HAVE_DEBUG has been removed; the Hazard3 Debug Module is always enabled)
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endif
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SOC ?= MINI
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SIMU ?= VCS
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SYNTH ?= NONE
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STA ?= NONE
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# HW
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PDK ?= IHP130
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HAVE_PLL ?= NO
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HAVE_SRAM_IF ?= NO
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HAVE_SRAM_MACRO ?= NO
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PDK_BEHAV ?= NO
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HAVE_SVA ?= NO
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BUILD_RELEASE ?= NO
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JTAG_IDCODE ?= DEADBEEF
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EXT_CLK_HZ ?= 72000000
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AUD_CLK_HZ ?= 18432000
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CLINT_TIMEBASE_HZ ?= 1000000
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WAVE ?= NO
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FORMAL ?= NO
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VCS_USE_LSF ?= YES
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REGRESS_NETSIM_BOOT_ONLY ?= NO
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RTL_SIM_TIMEOUT ?= -1
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SIM_FIRMWARE_NAME ?= $(FIRMWARE_NAME)
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SIM_SUCCESS_MARKER ?= SIM_TEST_PASS
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RTL_PATH := $(ROOT_PATH)/rtl/mini
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RTL_TOP ?= retrosoc_tb
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# SW
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ISA ?= RV32IM
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HAVE_CSR ?= NO
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FIRMWARE_NAME ?= retrosoc_fw
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APP ?= shell
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LINK_TYPE ?= ld2_sram
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COREMARK_MODE ?= quick
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BUILD_ROOT ?= $(ROOT_PATH)/build
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CACHE_ROOT ?= $(ROOT_PATH)/.cache/retrosoc
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BUILD_TIMESTAMP ?= $(shell date '+%Y-%m-%d-%H-%M')
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MAX_JOBS ?= 16
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HOST_CC ?= cc
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PYTHON ?= python3
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FLOW_PYTHON ?= $(PYTHON)
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CLANG_FORMAT ?= clang-format-14
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MBAKE ?= mbake
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VERIBLE_FORMAT ?= verible-verilog-format
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VERIBLE_LINT ?= verible-verilog-lint
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VCS_DEFAULT_RUNNER := $(if $(filter YES,$(VCS_USE_LSF)),bsub -Is)
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VCS_RUNNER ?= $(VCS_DEFAULT_RUNNER)
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VCS_SHELL_GOALS := comp sim netcomp netsim postcomp postsim
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VCS_SHELL_PYTHON := $(if $(filter VCS,$(SIMU)),$(if $(filter $(VCS_SHELL_GOALS),$(MAKECMDGOALS)),$(strip $(VCS_RUNNER) $(PYTHON)),$(PYTHON)),$(PYTHON))
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JOBS ?= $(shell count=$$(nproc 2>/dev/null || printf '1'); \
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if [ "$$count" -gt "$(MAX_JOBS)" ]; then printf '%s' '$(MAX_JOBS)'; \
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else printf '%s' "$$count"; fi)
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CONFIG_KEY_VARS := SOC PDK HAVE_PLL HAVE_SRAM_IF HAVE_SRAM_MACRO PDK_BEHAV HAVE_SVA \
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BUILD_RELEASE JTAG_IDCODE EXT_CLK_HZ AUD_CLK_HZ CLINT_TIMEBASE_HZ ISA HAVE_CSR APP LINK_TYPE \
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COREMARK_MODE RTL_TOP FIRMWARE_NAME
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VARIANT_ID := $(strip $(shell $(VCS_SHELL_PYTHON) $(ROOT_PATH)/scripts/config_key.py \
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--lock $(LOCK_FILE) --profile $(PROFILE_NAME) --timestamp $(BUILD_TIMESTAMP) \
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$(foreach var,$(CONFIG_KEY_VARS),--value $(var)=$($(var))) | tail -n 1))
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ifeq ($(VARIANT_ID),)
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$(error Failed to calculate build variant ID)
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endif
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LOCK_DIGEST := $(strip $(shell $(VCS_SHELL_PYTHON) $(ROOT_PATH)/scripts/dependency_lock.py \
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--lock $(LOCK_FILE) --digest | tail -n 1))
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CONFIG_DIGEST := $(lastword $(subst -, ,$(VARIANT_ID)))
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export BUILD_TIMESTAMP
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VARIANT_ROOT := $(abspath $(BUILD_ROOT))/$(VARIANT_ID)
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SW_BUILD_DIR := $(VARIANT_ROOT)/sw
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SIM_TOOL_NAME := $(shell printf '%s' '$(SIMU)' | tr '[:upper:]' '[:lower:]')
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SIM_BUILD_ROOT := $(VARIANT_ROOT)/sim/$(SIM_TOOL_NAME)
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SYN_BUILD_ROOT := $(VARIANT_ROOT)/syn/yosys
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STA_BUILD_ROOT := $(VARIANT_ROOT)/sta/opensta
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META_DIR := $(VARIANT_ROOT)/meta
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ifeq ($(SYNTH),YOSYS)
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FLOW_FILELIST_DIR := $(SYN_BUILD_ROOT)/filelists
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else
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FLOW_FILELIST_DIR := $(SIM_BUILD_ROOT)/filelists
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endif
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VALID_SOC := MINI
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VALID_SIMU := VCS VERILATOR IVERILOG
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VALID_SYNTH := NONE YOSYS
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VALID_STA := NONE OPENSTA
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VALID_PDK := ICS55 IHP130 SKY130 GF180
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VALID_BOOL := YES NO
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VALID_ISA := RV32E RV32I RV32IM
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VALID_APP := benchmark bringup ci_smoke coremark debug shell
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VALID_LINK_TYPE := xip ld2_all_sram ld2_sram ld2_psram ld2_sdram
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VALID_COREMARK_MODE := quick standard
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define validate_value
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$(if $(filter $($(1)),$(2)),,$(error Invalid $(1)='$($(1))'; expected one of: $(2)))
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endef
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$(call validate_value,SOC,$(VALID_SOC))
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$(call validate_value,SIMU,$(VALID_SIMU))
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$(call validate_value,SYNTH,$(VALID_SYNTH))
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$(call validate_value,STA,$(VALID_STA))
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$(call validate_value,PDK,$(VALID_PDK))
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$(call validate_value,HAVE_PLL,$(VALID_BOOL))
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$(call validate_value,HAVE_SRAM_IF,$(VALID_BOOL))
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$(call validate_value,HAVE_SRAM_MACRO,$(VALID_BOOL))
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$(call validate_value,PDK_BEHAV,$(VALID_BOOL))
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$(call validate_value,HAVE_SVA,$(VALID_BOOL))
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$(call validate_value,BUILD_RELEASE,$(VALID_BOOL))
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$(call validate_value,WAVE,$(VALID_BOOL))
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$(call validate_value,FORMAL,$(VALID_BOOL))
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$(call validate_value,VCS_USE_LSF,$(VALID_BOOL))
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$(call validate_value,REGRESS_NETSIM_BOOT_ONLY,$(VALID_BOOL))
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$(call validate_value,ISA,$(VALID_ISA))
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$(call validate_value,HAVE_CSR,$(VALID_BOOL))
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$(call validate_value,APP,$(VALID_APP))
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$(call validate_value,LINK_TYPE,$(VALID_LINK_TYPE))
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$(call validate_value,COREMARK_MODE,$(VALID_COREMARK_MODE))
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JTAG_IDCODE_VALID := $(shell printf '%s' '$(JTAG_IDCODE)' | grep -E '^[[:xdigit:]]{8}$$')
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ifneq ($(JTAG_IDCODE_VALID),$(JTAG_IDCODE))
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$(error JTAG_IDCODE='$(JTAG_IDCODE)' must be exactly eight hexadecimal digits)
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endif
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JTAG_IDCODE_DEC := $(shell value=$$(printf '%u' 0x$(JTAG_IDCODE)); \
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if [ $$value -gt 2147483647 ]; then echo $$((value - 4294967296)); else echo $$value; fi)
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EXT_CLK_HZ_VALID := $(shell printf '%s' '$(EXT_CLK_HZ)' | grep -E '^[1-9][[:digit:]]*$$')
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ifneq ($(EXT_CLK_HZ_VALID),$(EXT_CLK_HZ))
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$(error EXT_CLK_HZ='$(EXT_CLK_HZ)' must be a positive integer)
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endif
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AUD_CLK_HZ_VALID := $(shell printf '%s' '$(AUD_CLK_HZ)' | grep -E '^[1-9][[:digit:]]*$$')
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ifneq ($(AUD_CLK_HZ_VALID),$(AUD_CLK_HZ))
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$(error AUD_CLK_HZ='$(AUD_CLK_HZ)' must be a positive integer)
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endif
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CLINT_TIMEBASE_HZ_VALID := $(shell printf '%s' '$(CLINT_TIMEBASE_HZ)' | grep -E '^[1-9][[:digit:]]*$$')
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ifneq ($(CLINT_TIMEBASE_HZ_VALID),$(CLINT_TIMEBASE_HZ))
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$(error CLINT_TIMEBASE_HZ='$(CLINT_TIMEBASE_HZ)' must be a positive integer)
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endif
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CLINT_TIMEBASE_RATIO_VALID := $(shell if [ '$(EXT_CLK_HZ)' -ge '$(CLINT_TIMEBASE_HZ)' ] && \
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[ $$(( $(EXT_CLK_HZ) % $(CLINT_TIMEBASE_HZ) )) -eq 0 ]; then printf YES; fi)
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ifneq ($(CLINT_TIMEBASE_RATIO_VALID),YES)
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$(error EXT_CLK_HZ must be an integer multiple of CLINT_TIMEBASE_HZ)
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endif
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ifneq ($(filter benchmark-report,$(MAKECMDGOALS)),)
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ifneq ($(APP),benchmark)
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$(error benchmark-report requires APP=benchmark)
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endif
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ifneq ($(filter coremark-report,$(MAKECMDGOALS)),)
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ifneq ($(APP),coremark)
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$(error coremark-report requires APP=coremark)
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endif
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ifneq ($(COREMARK_MODE),quick)
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$(error coremark-report requires COREMARK_MODE=quick)
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endif
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endif
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ifeq ($(RTL_SIM_TIMEOUT),-1)
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RTL_SIM_TIMEOUT := 20000000
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endif
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endif
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ifeq ($(SYNTH),YOSYS)
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ifeq ($(filter $(PDK),IHP130 ICS55 GF180 SKY130),)
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$(error Yosys synthesis does not support PDK=$(PDK))
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endif
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endif
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ifeq ($(STA),OPENSTA)
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ifeq ($(HAVE_PLL),YES)
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$(error STA=OPENSTA requires a qualified PDK PLL timing profile; HAVE_PLL=YES is unsupported)
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endif
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endif
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DEF_LIST ?= +define+PDK_$(PDK)
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DEF_LIST += +define+SIMU_$(SIMU)
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DEF_LIST += +define+SOC_JTAG_IDCODE=$(JTAG_IDCODE_DEC)
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DEF_LIST += +define+SOC_EXT_CLK_HZ=$(EXT_CLK_HZ)
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DEF_LIST += +define+SOC_AUD_CLK_HZ=$(AUD_CLK_HZ)
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DEF_LIST += +define+SOC_CLINT_TIMEBASE_HZ=$(CLINT_TIMEBASE_HZ)
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ifeq ($(HAVE_PLL), YES)
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ifneq ($(filter $(PDK),GF180 SKY130),)
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$(error HAVE_PLL=YES requires a qualified crystal pad and is unsupported for PDK=$(PDK))
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endif
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DEF_LIST += +define+HAVE_PLL
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endif
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ifeq ($(HAVE_SRAM_IF), YES)
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DEF_LIST += +define+HAVE_SRAM_IF
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endif
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ifeq ($(HAVE_SRAM_MACRO), YES)
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DEF_LIST += +define+HAVE_SRAM_MACRO
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endif
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ifeq ($(PDK_BEHAV), YES)
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ifeq ($(SYNTH), YOSYS)
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$(error PDK_BEHAV=YES is for functional simulation and cannot be synthesized)
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endif
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DEF_LIST += +define+PDK_BEHAV
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endif
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ifeq ($(HAVE_SVA), NO)
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DEF_LIST += +define+SV_ASSRT_DISABLE
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endif
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ifeq ($(SYNTH), YOSYS)
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DEF_LIST += +define+SYNTHESIS
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endif
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include rtl/mini/Makefile
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include rtl/mini/mk/formal.mk
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ifeq ($(SIMU),IVERILOG)
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PERF_LOG ?= $(IVERILOG_BEHV_DIR)/sim.log
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else
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PERF_LOG ?= $(SIM_BUILD_ROOT)/sim.log
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endif
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ifeq ($(SYNTH), YOSYS)
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include syn/yosys/yosys.mk
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endif
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ifeq ($(STA), OPENSTA)
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include sta/opensta/opensta.mk
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endif
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.PHONY: help config doctor setup setup-regression setup-mpw setup-clusterip setup-ip setup-pdk setup-app \
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clean-all purge-cache manifest check-warnings metrics check-metrics package \
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regress-smoke regress-pr regress-nightly sim-asm format format-check sw-format sw-format-check mk-format \
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mk-format-check rtl-format rtl-format-check rtl-style-check rtl-migrate-connections rtl-migrate-names sw-policy-check sw-host-test \
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benchmark-report coremark-report \
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pin-map check-pin-map soc-topology check-soc-topology user-extensions check-user-extensions \
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check-clock-reset-domains tech-cell-test rtl-lint check-rtl-lint \
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formal formal-bus formal-rib-adapter formal-rib2apb formal-gpio formal-ws2812 formal-uart formal-i2c formal-timer formal-dvp formal-clean formal-doctor
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.NOTPARALLEL: setup
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help:
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@printf '%s\n' \
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'retroSoC build targets:' \
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' firmware | asm build firmware' \
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' comp | sim behavioral simulation' \
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' sim-asm build/run the assembly self-test' \
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' debug-sim run the Hazard3 Verilator/OpenOCD/GDB acceptance flow' \
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' netcomp | netsim synthesized-netlist simulation' \
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' postcomp | postsim post-layout simulation' \
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' synth | sta synthesis and timing analysis' \
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' setup install pinned external dependencies' \
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' setup-regression install pinned dependencies for all PR PDK profiles' \
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' doctor check tools, paths, and selected configuration' \
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' config | manifest print/write the effective configuration' \
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' memory-map generate the selected address-map artifacts' \
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' check-memory-map validate the canonical address map' \
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' pin-map generate the selected pin-map artifacts' \
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' check-pin-map validate the canonical SoC pin map' \
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' soc-topology generate the selected internal SoC integration artifacts' \
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' check-soc-topology validate the canonical internal SoC integration map' \
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' user-extensions generate the selected scalar user-extension bindings' \
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' check-user-extensions validate the canonical user-extension map' \
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' check-clock-reset-domains validate the root clock/reset and CDC inventory' \
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' rtl-lint | check-rtl-lint run/check strict Verilator RTL lint warnings' \
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' formal | formal-bus | formal-rib-adapter | formal-rib2apb run SBY protocol proofs' \
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' formal-sysctrl | formal-pll-rcu | formal-gpio | formal-ws2812 | formal-uart | formal-i2c | formal-timer | formal-clint | formal-dvp run peripheral proofs' \
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' formal-doctor check the SBY, Yosys, sv2v, and Bitwuzla formal toolchain' \
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' benchmark-report run the memory/DMA profile and write meta/performance.json' \
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' coremark-report run the quick CoreMark profile and write meta/coremark.json' \
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' tech-cell-test test GF180/SKY130 technology IO and clock wrappers' \
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' check-warnings | metrics analyze flow logs and reports' \
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' check-metrics apply the committed metrics policy' \
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' format format self-owned C, Makefile, and RTL sources' \
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' format-check check self-owned C, Makefile, and RTL formatting' \
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' sw-format apply clang-format to self-owned embedded C code' \
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' sw-format-check check embedded C whitespace and line-ending policy' \
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' mk-format | mk-format-check apply/check tracked Makefile formatting' \
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' rtl-format | rtl-format-check apply/check self-owned RTL formatting' \
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' rtl-migrate-connections convert provably positional RTL instances to named ports' \
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' rtl-migrate-names shorten local RTL identifier names' \
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' rtl-style-check check changed self-owned RTL naming and connections' \
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' sw-policy-check check embedded C API and naming policy' \
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' sw-host-test run host tests for deterministic SDK utilities' \
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' regress-smoke run the IHP130 fast regression suite' \
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' regress-pr | regress-nightly run supported full regression suites' \
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' package create checksummed source deliverables' \
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' clean | clean-all clean current flow or all build output' \
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' purge-cache remove dependency and compiler caches' \
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'' \
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'Usage: make CONFIG=configs/ci/ihp130.mk SIMU=IVERILOG sim'
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config:
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@printf '%-18s %s\n' \
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ROOT_PATH '$(ROOT_PATH)' CONFIG '$(or $(CONFIG_PATH),<defaults>)' \
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BUILD_TIMESTAMP '$(BUILD_TIMESTAMP)' VARIANT_ID '$(VARIANT_ID)' VARIANT_ROOT '$(VARIANT_ROOT)' \
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JOBS '$(JOBS)' \
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SOC '$(SOC)' MGMT_CORE 'HAZARD3' \
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SIMU '$(SIMU)' SYNTH '$(SYNTH)' STA '$(STA)' FORMAL '$(FORMAL)' \
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VCS_USE_LSF '$(VCS_USE_LSF)' PDK '$(PDK)' \
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HAVE_PLL '$(HAVE_PLL)' HAVE_SRAM_IF '$(HAVE_SRAM_IF)' \
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HAVE_SRAM_MACRO '$(HAVE_SRAM_MACRO)' PDK_BEHAV '$(PDK_BEHAV)' HAVE_SVA '$(HAVE_SVA)' \
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BUILD_RELEASE '$(BUILD_RELEASE)' \
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JTAG_IDCODE '$(JTAG_IDCODE)' EXT_CLK_HZ '$(EXT_CLK_HZ)' AUD_CLK_HZ '$(AUD_CLK_HZ)' \
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CLINT_TIMEBASE_HZ '$(CLINT_TIMEBASE_HZ)' \
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ISA '$(ISA)' HAVE_CSR '$(HAVE_CSR)' APP '$(APP)' \
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LINK_TYPE '$(LINK_TYPE)' COREMARK_MODE '$(COREMARK_MODE)'
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doctor:
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@python3 $(ROOT_PATH)/scripts/doctor.py \
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--root $(ROOT_PATH) --simu $(SIMU) --synth $(SYNTH) --sta $(STA) \
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--pdk $(PDK) --formal $(FORMAL) --lock $(LOCK_FILE)
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benchmark-report: firmware
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$(MAKE) RTL_SIM_TIMEOUT=$(RTL_SIM_TIMEOUT) sim
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$(FLOW_PYTHON) $(ROOT_PATH)/scripts/parse_performance_log.py --log $(PERF_LOG) \
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--output $(META_DIR)/performance.json
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coremark-report: firmware
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$(MAKE) RTL_SIM_TIMEOUT=$(RTL_SIM_TIMEOUT) sim
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$(FLOW_PYTHON) $(ROOT_PATH)/scripts/parse_coremark_log.py --log $(PERF_LOG) \
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--output $(META_DIR)/coremark.json
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setup: setup-mpw setup-clusterip setup-ip setup-pdk setup-app
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setup-regression:
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$(MAKE) CONFIG=configs/ci/ihp130.mk setup
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$(MAKE) CONFIG=configs/ci/gf180.mk setup
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$(MAKE) CONFIG=configs/ci/ics55.mk setup
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$(MAKE) CONFIG=configs/ci/sky130.mk setup
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setup-mpw:
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python3 $(ROOT_PATH)/setup.py
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python3 $(ROOT_PATH)/scripts/prepare_mpw.py \
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--lock-file $(CACHE_ROOT)/locks/mpw-prepare.lock
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@mkdir -p $(dir $(MPW_STAMP))
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@touch $(MPW_STAMP)
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setup-clusterip:
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python3 $(ROOT_PATH)/rtl/managed/clusterip/setup.py
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setup-ip:
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python3 $(ROOT_PATH)/rtl/ip/setup.py
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setup-pdk:
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python3 $(ROOT_PATH)/pdk/setup.py --pdk $(PDK)
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setup-app:
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python3 $(ROOT_PATH)/app/setup.py
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clean-all:
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python3 $(ROOT_PATH)/scripts/clean.py --root $(ROOT_PATH) --path $(abspath $(BUILD_ROOT))
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purge-cache:
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python3 $(ROOT_PATH)/scripts/clean.py --root $(ROOT_PATH) --path $(abspath $(CACHE_ROOT))
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manifest:
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$(FLOW_PYTHON) $(ROOT_PATH)/scripts/manifest.py create --root $(ROOT_PATH) \
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--lock $(LOCK_FILE) --output $(META_DIR)/manifest.json --profile $(PROFILE_NAME) \
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$(foreach var,$(CONFIG_KEY_VARS),--config $(var)=$($(var))) \
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--config SIMU=$(SIMU) --config SYNTH=$(SYNTH) --config STA=$(STA)
|
|
|
|
check-warnings:
|
|
python3 $(ROOT_PATH)/scripts/analyze_warnings.py check --root $(ROOT_PATH) \
|
|
--profile $(PROFILE_NAME) --variant-root $(VARIANT_ROOT) --output $(META_DIR)/warnings.json
|
|
|
|
metrics:
|
|
python3 $(ROOT_PATH)/scripts/metrics.py collect --variant-root $(VARIANT_ROOT) \
|
|
--output $(META_DIR)/metrics.json
|
|
|
|
check-metrics: metrics
|
|
python3 $(ROOT_PATH)/scripts/metrics.py check --metrics $(META_DIR)/metrics.json \
|
|
--policy $(ROOT_PATH)/quality/metrics/policy.json \
|
|
--baseline $(ROOT_PATH)/quality/metrics/baseline.json
|
|
|
|
sw-format:
|
|
python3 $(ROOT_PATH)/scripts/check_embedded_c.py --root $(ROOT_PATH) \
|
|
--apply-format --clang-format $(CLANG_FORMAT)
|
|
|
|
sw-format-check:
|
|
python3 $(ROOT_PATH)/scripts/check_embedded_c.py --root $(ROOT_PATH) --format-check \
|
|
--clang-format-check --clang-format $(CLANG_FORMAT)
|
|
|
|
format: sw-format mk-format rtl-format
|
|
|
|
format-check: sw-format-check mk-format-check rtl-format-check rtl-style-check
|
|
|
|
mk-format:
|
|
python3 $(ROOT_PATH)/scripts/check_format.py --root $(ROOT_PATH) --kind make --apply \
|
|
--mbake $(MBAKE)
|
|
|
|
mk-format-check:
|
|
python3 $(ROOT_PATH)/scripts/check_format.py --root $(ROOT_PATH) --kind make \
|
|
--mbake $(MBAKE)
|
|
|
|
rtl-format:
|
|
python3 $(ROOT_PATH)/scripts/check_format.py --root $(ROOT_PATH) --kind rtl --apply \
|
|
--verible-verilog-format $(VERIBLE_FORMAT)
|
|
|
|
rtl-format-check:
|
|
python3 $(ROOT_PATH)/scripts/check_format.py --root $(ROOT_PATH) --kind rtl \
|
|
--verible-verilog-format $(VERIBLE_FORMAT)
|
|
|
|
rtl-migrate-connections:
|
|
python3 $(ROOT_PATH)/scripts/migrate_rtl_connections.py --root $(ROOT_PATH) --apply
|
|
|
|
rtl-migrate-names:
|
|
python3 $(ROOT_PATH)/scripts/migrate_rtl_names.py --root $(ROOT_PATH) --apply
|
|
|
|
rtl-style-check:
|
|
python3 $(ROOT_PATH)/scripts/check_rtl_style.py --root $(ROOT_PATH) \
|
|
--profile owned --changed-only --verible-verilog-lint $(VERIBLE_LINT)
|
|
|
|
sw-policy-check:
|
|
python3 $(ROOT_PATH)/scripts/check_embedded_c.py --root $(ROOT_PATH) --policy-check
|
|
|
|
sw-host-test:
|
|
python3 $(ROOT_PATH)/scripts/run_c_tests.py --root $(ROOT_PATH) --cc $(HOST_CC)
|
|
|
|
package: $(MPW_VARIANT_STAMP) $(FILELIST_STAMP) manifest
|
|
python3 $(ROOT_PATH)/scripts/package.py --root $(ROOT_PATH) --lock $(LOCK_FILE) \
|
|
--variant-root $(VARIANT_ROOT) --output-dir $(ROOT_PATH)/dist/$(VARIANT_ID)
|
|
|
|
regress-smoke:
|
|
python3 $(ROOT_PATH)/scripts/regress.py --root $(ROOT_PATH) --suite smoke --pdk IHP130
|
|
|
|
regress-pr:
|
|
python3 $(ROOT_PATH)/scripts/regress.py --root $(ROOT_PATH) --suite pr --pdk IHP130 $(if $(filter YES,$(REGRESS_NETSIM_BOOT_ONLY)),--netsim-boot-only)
|
|
python3 $(ROOT_PATH)/scripts/regress.py --root $(ROOT_PATH) --suite pr --pdk GF180 $(if $(filter YES,$(REGRESS_NETSIM_BOOT_ONLY)),--netsim-boot-only)
|
|
python3 $(ROOT_PATH)/scripts/regress.py --root $(ROOT_PATH) --suite pr --pdk SKY130 $(if $(filter YES,$(REGRESS_NETSIM_BOOT_ONLY)),--netsim-boot-only)
|
|
python3 $(ROOT_PATH)/scripts/regress.py --root $(ROOT_PATH) --suite pr --pdk ICS55 $(if $(filter YES,$(REGRESS_NETSIM_BOOT_ONLY)),--netsim-boot-only)
|
|
|
|
regress-nightly:
|
|
python3 $(ROOT_PATH)/scripts/regress.py --root $(ROOT_PATH) --suite nightly
|
|
|
|
sim-asm: asm
|
|
$(MAKE) SIM_FIRMWARE_NAME=$(ASM_FIRMWARE_NAME) sim
|